diff --git a/generators/firechip/src/main/scala/SimConfigs.scala b/generators/firechip/src/main/scala/SimConfigs.scala
index 1118fe07..937c2877 100644
--- a/generators/firechip/src/main/scala/SimConfigs.scala
+++ b/generators/firechip/src/main/scala/SimConfigs.scala
@@ -52,3 +52,7 @@ class FireSimDDR3FRFCFSLLC4MB3ClockDivConfig extends Config(
   new FRFCFS16GBQuadRankLLC4MB3Div ++
   new FireSimConfig)
 
+class Midas2Config extends Config(
+  new WithMultiCycleRamModels ++
+  new FireSimConfig)
+
diff --git a/generators/firechip/src/main/scala/TargetMixins.scala b/generators/firechip/src/main/scala/TargetMixins.scala
index 199a22cc..f36cf021 100644
--- a/generators/firechip/src/main/scala/TargetMixins.scala
+++ b/generators/firechip/src/main/scala/TargetMixins.scala
@@ -1,6 +1,7 @@
 package firesim.firesim
 
 import chisel3._
+import chisel3.experimental.annotate
 import freechips.rocketchip.config.{Field, Parameters}
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.tilelink._
@@ -12,7 +13,7 @@ import freechips.rocketchip.rocket.TracedInstruction
 import firesim.endpoints.{TraceOutputTop, DeclockedTracedInstruction}
 
 import midas.models.AXI4BundleWithEdge
-import midas.targetutils.ExcludeInstanceAsserts
+import midas.targetutils.{ExcludeInstanceAsserts, MemModelAnnotation}
 
 /** Copied from RC and modified to change the IO type of the Imp to include the Diplomatic edges
   *  associated with each port. This drives FASED functional model sizing
@@ -103,3 +104,24 @@ trait HasTraceIOImp extends LazyModuleImp {
 trait ExcludeInvalidBoomAssertions extends LazyModuleImp {
   ExcludeInstanceAsserts(("NonBlockingDCache", "dtlb"))
 }
+
+trait CanHaveMultiCycleRegfileImp {
+  val outer: utilities.HasBoomAndRocketTiles
+  val boomCores = outer.boomTiles.map(tile => tile.module.core)
+  boomCores.foreach({ core =>
+    core.iregfile match {
+      case irf: boom.exu.RegisterFileSynthesizable => annotate(MemModelAnnotation(irf.regfile))
+      case _ => Nil
+    }
+
+     if (core.fp_pipeline != null) core.fp_pipeline.fregfile match {
+      case irf: boom.exu.RegisterFileSynthesizable => annotate(MemModelAnnotation(irf.regfile))
+      case _ => Nil
+    }
+  })
+
+  outer.rocketTiles.foreach({ tile =>
+    annotate(MemModelAnnotation(tile.module.core.rocketImpl.rf.rf))
+    tile.module.fpuOpt.foreach(fpu => annotate(MemModelAnnotation(fpu.fpuImpl.regfile)))
+  })
+}
diff --git a/generators/firechip/src/main/scala/Targets.scala b/generators/firechip/src/main/scala/Targets.scala
index ba966fac..37c1f2b1 100644
--- a/generators/firechip/src/main/scala/Targets.scala
+++ b/generators/firechip/src/main/scala/Targets.scala
@@ -31,7 +31,7 @@ import java.io.File
 * determine which driver to build.
 *******************************************************************************/
 
-class FireSim(implicit p: Parameters) extends RocketSubsystem
+class FireSim(implicit p: Parameters) extends Subsystem
     with HasHierarchicalBusTopology
     with CanHaveFASEDOptimizedMasterAXI4MemPort
     with HasPeripheryBootROM
@@ -45,7 +45,7 @@ class FireSim(implicit p: Parameters) extends RocketSubsystem
   override lazy val module = new FireSimModuleImp(this)
 }
 
-class FireSimModuleImp[+L <: FireSim](l: L) extends RocketSubsystemModuleImp(l)
+class FireSimModuleImp[+L <: FireSim](l: L) extends SubsystemModuleImp(l)
     with HasRTCModuleImp
     with CanHaveFASEDOptimizedMasterAXI4MemPortModuleImp
     with HasPeripheryBootROMModuleImp
@@ -55,9 +55,10 @@ class FireSimModuleImp[+L <: FireSim](l: L) extends RocketSubsystemModuleImp(l)
     with HasPeripheryIceNICModuleImpValidOnly
     with HasPeripheryBlockDeviceModuleImp
     with HasTraceIOImp
+    with CanHaveMultiCycleRegfileImp
 
 
-class FireSimNoNIC(implicit p: Parameters) extends RocketSubsystem
+class FireSimNoNIC(implicit p: Parameters) extends Subsystem
     with HasHierarchicalBusTopology
     with CanHaveFASEDOptimizedMasterAXI4MemPort
     with HasPeripheryBootROM
@@ -70,7 +71,7 @@ class FireSimNoNIC(implicit p: Parameters) extends RocketSubsystem
   override lazy val module = new FireSimNoNICModuleImp(this)
 }
 
-class FireSimNoNICModuleImp[+L <: FireSimNoNIC](l: L) extends RocketSubsystemModuleImp(l)
+class FireSimNoNICModuleImp[+L <: FireSimNoNIC](l: L) extends SubsystemModuleImp(l)
     with HasRTCModuleImp
     with CanHaveFASEDOptimizedMasterAXI4MemPortModuleImp
     with HasPeripheryBootROMModuleImp
@@ -79,6 +80,7 @@ class FireSimNoNICModuleImp[+L <: FireSimNoNIC](l: L) extends RocketSubsystemMod
     with HasPeripheryUARTModuleImp
     with HasPeripheryBlockDeviceModuleImp
     with HasTraceIOImp
+    with CanHaveMultiCycleRegfileImp
 
 
 class FireBoom(implicit p: Parameters) extends Subsystem
@@ -106,6 +108,7 @@ class FireBoomModuleImp[+L <: FireBoom](l: L) extends SubsystemModuleImp(l)
     with HasPeripheryBlockDeviceModuleImp
     with HasTraceIOImp
     with ExcludeInvalidBoomAssertions
+    with CanHaveMultiCycleRegfileImp
 
 class FireBoomNoNIC(implicit p: Parameters) extends Subsystem
     with HasHierarchicalBusTopology
@@ -130,6 +133,7 @@ class FireBoomNoNICModuleImp[+L <: FireBoomNoNIC](l: L) extends SubsystemModuleI
     with HasPeripheryBlockDeviceModuleImp
     with HasTraceIOImp
     with ExcludeInvalidBoomAssertions
+    with CanHaveMultiCycleRegfileImp
 
 case object NumNodes extends Field[Int]
 
diff --git a/generators/firechip/src/test/scala/ScalaTestSuite.scala b/generators/firechip/src/test/scala/ScalaTestSuite.scala
index 54848ac8..44c4bff0 100644
--- a/generators/firechip/src/test/scala/ScalaTestSuite.scala
+++ b/generators/firechip/src/test/scala/ScalaTestSuite.scala
@@ -109,9 +109,9 @@ abstract class FireSimTestSuite(
         val lines = Source.fromFile(file).getLines.toList
         lines.filter(_.startsWith("TRACEPORT")).drop(dropLines)
       }
-      val resetLength = 50
+      val resetLength = 51
       val verilatedOutput  = getLines(new File(outDir,  s"/${verilatedLog}"))
-      val synthPrintOutput = getLines(new File(genDir, s"/TRACEFILE"), resetLength + 1)
+      val synthPrintOutput = getLines(new File(genDir, s"/TRACEFILE"), resetLength)
       assert(verilatedOutput.size == synthPrintOutput.size, "Outputs differ in length")
       assert(verilatedOutput.nonEmpty)
       for ( (vPrint, sPrint) <- verilatedOutput.zip(synthPrintOutput) ) {
@@ -131,8 +131,9 @@ abstract class FireSimTestSuite(
 }
 
 class RocketF1Tests extends FireSimTestSuite("FireSimNoNIC", "FireSimRocketChipConfig", "FireSimConfig")
-class RocketF1ClockDivTests extends FireSimTestSuite("FireSimNoNIC", "FireSimRocketChipConfig", "FireSimClockDivConfig")
 class BoomF1Tests extends FireSimTestSuite("FireBoomNoNIC", "FireSimBoomConfig", "FireSimConfig")
 class RocketNICF1Tests extends FireSimTestSuite("FireSim", "FireSimRocketChipConfig", "FireSimConfig") {
   runSuite("verilator")(NICLoopbackTests)
 }
+class RamModelRocketF1Tests extends FireSimTestSuite("FireSimNoNIC", "FireSimRocketChipDualCoreConfig", "Midas2Config")
+class RamModelBoomF1Tests extends FireSimTestSuite("FireBoomNoNIC", "FireSimBoomConfig", "Midas2Config")
diff --git a/sims/firesim b/sims/firesim
index 4116a8f2..92fe0e4d 160000
--- a/sims/firesim
+++ b/sims/firesim
@@ -1 +1 @@
-Subproject commit 4116a8f2985906a962f2cd49ba4735479ea1ea0a
+Subproject commit 92fe0e4def4d9bde0c5c36cd9090ef8c60fd0d45