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[skip ci] address comments, instantiate Sha3Accel module

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Harrison Liew
2019-09-27 09:37:27 -07:00
parent 8fffc1c670
commit 35566195db
3 changed files with 28 additions and 120 deletions
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8
docs/VLSI/Advanced-Usage.rst
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@@ -5,14 +5,14 @@ Advanced Usage
Alternative RTL Flows
---------------------
The Make-based build system provided supports using Hammer without using RTL generated by Chipyard. To push a custom verilog module through, one only needs to export the following environment variables before ``make buildfile``.
The Make-based build system provided supports using Hammer without using RTL generated by Chipyard. To push a custom verilog module through, one only needs to give the following environment variables ``make buildfile`` (or edit them directly in the Makefile).
.. code-block:: shell
export CUSTOM_VLOG=<your verilog files>
export VLSI_TOP=<your top module>
CUSTOM_VLOG=<your verilog files>
VLSI_TOP=<your top module>
``CUSTOM_VLOG`` breaks the dependency on the rest of the
``CUSTOM_VLOG`` breaks the dependency on the rest of the Chipyard infrastructure and does not start any Chisel/FIRRTL elaboration. ``VLSI_TOP`` selects the top module from your custom Verilog files.
Under the Hood
--------------

13
docs/VLSI/Tutorial.rst
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@@ -2,7 +2,7 @@
ASAP7 Tutorial
==============
The ``vlsi`` folder of this repository contains an example HAMMER flow with the SHA-3 accelerator and a dummy hard macro in the ASAP7 PDK. It is intended for use with the Cadence and Mentor tool plugins.
The ``vlsi`` folder of this repository contains an example HAMMER flow with the SHA-3 accelerator and a dummy hard macro. This example tutorial uses the built-in ASAP7 technology plugin and requires access to the included Cadence and Mentor tool plugin submodules. Cadence is necessary for synthesis & place-and-route, while Mentor is needed for DRC & LVS.
Project Structure
-----------------
@@ -81,18 +81,15 @@ To elaborate the Sha3RocketConfig (Rocketchip w/ the accelerator) and set up all
.. code-block:: shell
export MACROCOMPILER_MODE='--mode synflops'
export CONFIG=Sha3RocketConfig
export VLSI_TOP=Sha3AccelwBB
make buildfile
make buildfile MACROCOMPILER_MODE='--mode synflops' CONFIG=Sha3RocketConfig VLSI_TOP=Sha3AccelwBB
The ``MACROCOMPILER_MODE='--mode synflops'`` is needed because the ASAP7 process does not yet have a memory compiler. Therefore, flip-flop arrays are used instead.
The ``CONFIG=Sha3RocketConfig`` selects the target generator config in the same manner as the rest of the Chipyard framework.
The ``CONFIG=Sha3RocketConfig`` selects the target generator config in the same manner as the rest of the Chipyard framework. This elaborates a Rocket-chip with the Sha3Accel module.
The ``VLSI_TOP=Sha3AccelwBB`` indicates that we are only interested in physical design of the accelerator block. If this variable is not set, the entire SoC will be pushed through physical design.
The ``VLSI_TOP=Sha3AccelwBB`` indicates that we are only interested in physical design of the accelerator block. If this variable is not set, the entire SoC will be pushed through physical design. Note that you should not set the ``TOP`` variable because it is used during Chisel elaboration.
For the curious, ``make buildfile`` generates a set of Make targets in ``build/hammer.d``. It needs to be re-run if environment variables are changed.
For the curious, ``make buildfile`` generates a set of Make targets in ``build/hammer.d``. It needs to be re-run if environment variables are changed. It is recommended that you edit these variables directly in the Makefile rather than exporting them to your shell environment.
Running the VLSI Flow
---------------------