From 352fa91b62785ceba1575f9093bbce7e42034a6e Mon Sep 17 00:00:00 2001 From: chick Date: Tue, 10 Aug 2021 15:28:25 -0700 Subject: [PATCH] IOCell toBool => asBool MacroCompiler needs more specific firrtl.Utils imports, Comment out legalize SynFlops more precise imports YamlHelpers use FileUtils ResetInverter LegacyModule => Module Retime use Module instead of LegacyModule YamlHelpers uses FileUtils instead of getResource ResetInvert use Module instead of LegacyModule Masks add scalatest wrappers for getting better test reports SpecificExamples drop tapeout prefix, and add scalatest blocks GenerateSpec, let ChiselStage emit the firrt directly to target dir, add some actual tests that files were created GenerateTopSpec use FileUtils FlipChipMacroSpec use FileUtils IOPropertiesSpec use FileUtils --- .../barstools/iocell/chisel/IOCell.scala | 2 +- .../barstools/macros/MacroCompiler.scala | 3 +- .../scala/barstools/macros/SynFlops.scala | 4 +- .../tapeout/transforms/ResetInverter.scala | 2 +- .../tapeout/transforms/retime/Retime.scala | 2 +- .../transforms/utils/YamlHelpers.scala | 7 +- .../src/main/scala/mdf/macrolib/Utils.scala | 11 ++- .../test/scala/barstools/macros/Masks.scala | 92 ++++++++++++++----- .../barstools/macros/SpecificExamples.scala | 25 +++-- .../tapeout/transforms/GenerateSpec.scala | 10 +- .../tapeout/transforms/GenerateTopSpec.scala | 3 +- .../mdf/macrolib/FlipChipMacroSpec.scala | 5 +- .../scala/mdf/macrolib/IOPropertiesSpec.scala | 5 +- 13 files changed, 118 insertions(+), 53 deletions(-) diff --git a/tapeout/src/main/scala/barstools/iocell/chisel/IOCell.scala b/tapeout/src/main/scala/barstools/iocell/chisel/IOCell.scala index d244d298..6d444936 100644 --- a/tapeout/src/main/scala/barstools/iocell/chisel/IOCell.scala +++ b/tapeout/src/main/scala/barstools/iocell/chisel/IOCell.scala @@ -141,7 +141,7 @@ object IOCell { * @param name An optional name or name prefix to use for naming IO cells * @return A Seq of all generated IO cell instances */ - val toSyncReset: (Reset) => Bool = _.toBool + val toSyncReset: (Reset) => Bool = _.asBool() val toAsyncReset: (Reset) => AsyncReset = _.asAsyncReset def generateFromSignal[T <: Data, R <: Reset]( coreSignal: T, diff --git a/tapeout/src/main/scala/barstools/macros/MacroCompiler.scala b/tapeout/src/main/scala/barstools/macros/MacroCompiler.scala index bfcf78da..6218b593 100644 --- a/tapeout/src/main/scala/barstools/macros/MacroCompiler.scala +++ b/tapeout/src/main/scala/barstools/macros/MacroCompiler.scala @@ -8,7 +8,7 @@ package barstools.macros import barstools.macros.Utils._ -import firrtl.Utils._ +import firrtl.Utils.{BoolType, one, zero} import firrtl.annotations._ import firrtl.ir._ import firrtl.stage.{FirrtlSourceAnnotation, FirrtlStage, Forms, OutputFileAnnotation, RunFirrtlTransformAnnotation} @@ -783,7 +783,6 @@ class MacroCompilerOptimizations extends SeqTransform with DependencyAPIMigratio new firrtl.transforms.ConstantPropagation, passes.memlib.VerilogMemDelays, new firrtl.transforms.ConstantPropagation, - passes.Legalize, passes.SplitExpressions, passes.CommonSubexpressionElimination ) diff --git a/tapeout/src/main/scala/barstools/macros/SynFlops.scala b/tapeout/src/main/scala/barstools/macros/SynFlops.scala index 5d39cda9..a6fe32a4 100644 --- a/tapeout/src/main/scala/barstools/macros/SynFlops.scala +++ b/tapeout/src/main/scala/barstools/macros/SynFlops.scala @@ -3,7 +3,7 @@ package barstools.macros import barstools.macros.Utils._ -import firrtl.Utils._ +import firrtl.Utils.{zero, one} import firrtl._ import firrtl.ir._ import firrtl.passes.MemPortUtils.memPortField @@ -27,7 +27,7 @@ class SynFlopsPass(synflops: Boolean, libs: Seq[Macro]) extends firrtl.passes.Pa case Some(gran) => (UIntType(IntWidth(gran)), gran.intValue) } - val maxDepth = min(lib.src.depth, 1 << 26) + val maxDepth = firrtl.Utils.min(lib.src.depth, 1 << 26) val numMems = lib.src.depth / maxDepth // Change macro to be mapped onto to look like the below mem diff --git a/tapeout/src/main/scala/barstools/tapeout/transforms/ResetInverter.scala b/tapeout/src/main/scala/barstools/tapeout/transforms/ResetInverter.scala index 33d2f78a..29c9f0da 100644 --- a/tapeout/src/main/scala/barstools/tapeout/transforms/ResetInverter.scala +++ b/tapeout/src/main/scala/barstools/tapeout/transforms/ResetInverter.scala @@ -60,7 +60,7 @@ class ResetInverterTransform extends Transform with DependencyAPIMigration { trait ResetInverter { self: chisel3.Module => - def invert[T <: chisel3.internal.LegacyModule](module: T): Unit = { + def invert[T <: chisel3.Module](module: T): Unit = { chisel3.experimental.annotate(new chisel3.experimental.ChiselAnnotation with RunFirrtlTransform { def transformClass: Class[_ <: Transform] = classOf[ResetInverterTransform] def toFirrtl: Annotation = ResetInverterAnnotation(module.toNamed) diff --git a/tapeout/src/main/scala/barstools/tapeout/transforms/retime/Retime.scala b/tapeout/src/main/scala/barstools/tapeout/transforms/retime/Retime.scala index 931af88d..1a9d6668 100644 --- a/tapeout/src/main/scala/barstools/tapeout/transforms/retime/Retime.scala +++ b/tapeout/src/main/scala/barstools/tapeout/transforms/retime/Retime.scala @@ -39,7 +39,7 @@ class RetimeTransform extends Transform with DependencyAPIMigration { trait RetimeLib { self: chisel3.Module => - def retime[T <: chisel3.internal.LegacyModule](module: T): Unit = { + def retime[T <: chisel3.Module](module: T): Unit = { chisel3.experimental.annotate(new chisel3.experimental.ChiselAnnotation with RunFirrtlTransform { def transformClass: Class[_ <: Transform] = classOf[RetimeTransform] def toFirrtl: Annotation = RetimeAnnotation(module.toNamed) diff --git a/tapeout/src/main/scala/barstools/tapeout/transforms/utils/YamlHelpers.scala b/tapeout/src/main/scala/barstools/tapeout/transforms/utils/YamlHelpers.scala index 9a226de5..9b58e083 100644 --- a/tapeout/src/main/scala/barstools/tapeout/transforms/utils/YamlHelpers.scala +++ b/tapeout/src/main/scala/barstools/tapeout/transforms/utils/YamlHelpers.scala @@ -1,5 +1,6 @@ package barstools.tapeout.transforms.utils +import firrtl.FileUtils import net.jcazevedo.moultingyaml._ import java.io.File @@ -10,10 +11,10 @@ class YamlFileReader(resource: String) { val yamlString = file match { case f if f.isEmpty => // Use example config if no file is provided - val stream = getClass.getResourceAsStream(resource) - io.Source.fromInputStream(stream).mkString + val stream = FileUtils.getTextResource(resource) + stream case f if new File(f).exists => - scala.io.Source.fromFile(f).getLines.mkString("\n") + FileUtils.getText(f) case _ => throw new Exception("No valid Yaml file found!") } diff --git a/tapeout/src/main/scala/mdf/macrolib/Utils.scala b/tapeout/src/main/scala/mdf/macrolib/Utils.scala index 795cff0a..86d78a24 100644 --- a/tapeout/src/main/scala/mdf/macrolib/Utils.scala +++ b/tapeout/src/main/scala/mdf/macrolib/Utils.scala @@ -1,6 +1,8 @@ package mdf.macrolib import play.api.libs.json._ + +import java.io.FileNotFoundException import scala.collection.mutable.ListBuffer import scala.language.implicitConversions @@ -37,7 +39,14 @@ object Utils { path match { case None => None // Read file into string and parse - case Some(p) => Utils.readMDFFromString(scala.io.Source.fromFile(p).mkString) + case Some(p) => + try { + Utils.readMDFFromString(scala.io.Source.fromFile(p).mkString) + } catch { + case f: FileNotFoundException => + println(s"FILE NOT FOUND $p in dir ${os.pwd}") + throw f + } } } diff --git a/tapeout/src/test/scala/barstools/macros/Masks.scala b/tapeout/src/test/scala/barstools/macros/Masks.scala index c472669a..43d6b3d6 100644 --- a/tapeout/src/test/scala/barstools/macros/Masks.scala +++ b/tapeout/src/test/scala/barstools/macros/Masks.scala @@ -27,7 +27,9 @@ class Masks_FourTypes_NonMaskedMem_NonMaskedLib override lazy val libWidth = 8 override lazy val libMaskGran = None - compileExecuteAndTest(mem, lib, v, output) + it should "compile, execute, and test" in { + compileExecuteAndTest(mem, lib, v, output) + } } class Masks_FourTypes_NonMaskedMem_MaskedLib @@ -40,7 +42,9 @@ class Masks_FourTypes_NonMaskedMem_MaskedLib override lazy val libWidth = 8 override lazy val libMaskGran = Some(2) - compileExecuteAndTest(mem, lib, v, output) + it should "compile, execute, and test" in { + compileExecuteAndTest(mem, lib, v, output) + } } class Masks_FourTypes_MaskedMem_NonMaskedLib @@ -53,7 +57,9 @@ class Masks_FourTypes_MaskedMem_NonMaskedLib override lazy val libWidth = 8 override lazy val libMaskGran = None - compileExecuteAndTest(mem, lib, v, output) + it should "compile, execute, and test" in { + compileExecuteAndTest(mem, lib, v, output) + } } class Masks_FourTypes_MaskedMem_NonMaskedLib_SmallerMaskGran @@ -66,7 +72,9 @@ class Masks_FourTypes_MaskedMem_NonMaskedLib_SmallerMaskGran override lazy val libWidth = 8 override lazy val libMaskGran = None - compileExecuteAndTest(mem, lib, v, output) + it should "compile, execute, and test" in { + compileExecuteAndTest(mem, lib, v, output) + } } class Masks_FourTypes_MaskedMem_MaskedLib @@ -79,7 +87,9 @@ class Masks_FourTypes_MaskedMem_MaskedLib override lazy val libWidth = 16 override lazy val libMaskGran = Some(4) - compileExecuteAndTest(mem, lib, v, output) + it should "compile, execute, and test" in { + compileExecuteAndTest(mem, lib, v, output) + } } class Masks_FourTypes_MaskedMem_MaskedLib_SameMaskGran @@ -92,7 +102,9 @@ class Masks_FourTypes_MaskedMem_MaskedLib_SameMaskGran override lazy val libWidth = 16 override lazy val libMaskGran = Some(8) - compileExecuteAndTest(mem, lib, v, output) + it should "compile, execute, and test" in { + compileExecuteAndTest(mem, lib, v, output) + } } class Masks_FourTypes_MaskedMem_MaskedLib_SmallerMaskGran @@ -105,7 +117,9 @@ class Masks_FourTypes_MaskedMem_MaskedLib_SmallerMaskGran override lazy val libWidth = 32 override lazy val libMaskGran = Some(8) - compileExecuteAndTest(mem, lib, v, output) + it should "compile, execute, and test" in { + compileExecuteAndTest(mem, lib, v, output) + } } // Bit-mask memories to non-masked libs whose width is larger than 1. @@ -117,7 +131,9 @@ class Masks_BitMaskedMem_NonMaskedLib extends MacroCompilerSpec with HasSRAMGene override lazy val libWidth = 8 override lazy val libMaskGran = None - compileExecuteAndTest(mem, lib, v, output) + it should "compile, execute, and test" in { + compileExecuteAndTest(mem, lib, v, output) + } } // FPGA-style byte-masked memories. @@ -131,7 +147,9 @@ class Masks_FPGAStyle_32_8 override lazy val memMaskGran = Some(32) override lazy val libMaskGran = Some(8) - compileExecuteAndTest(mem, lib, v, output) + it should "compile, execute, and test" in { + compileExecuteAndTest(mem, lib, v, output) + } } // Simple powers of two with bit-masked lib. @@ -145,7 +163,9 @@ class Masks_PowersOfTwo_8_1 override lazy val memMaskGran = Some(8) override lazy val libMaskGran = Some(1) - compileExecuteAndTest(mem, lib, v, output) + it should "compile, execute, and test" in { + compileExecuteAndTest(mem, lib, v, output) + } } class Masks_PowersOfTwo_16_1 @@ -157,7 +177,9 @@ class Masks_PowersOfTwo_16_1 override lazy val memMaskGran = Some(16) override lazy val libMaskGran = Some(1) - compileExecuteAndTest(mem, lib, v, output) + it should "compile, execute, and test" in { + compileExecuteAndTest(mem, lib, v, output) + } } class Masks_PowersOfTwo_32_1 @@ -169,7 +191,9 @@ class Masks_PowersOfTwo_32_1 override lazy val memMaskGran = Some(32) override lazy val libMaskGran = Some(1) - compileExecuteAndTest(mem, lib, v, output) + it should "compile, execute, and test" in { + compileExecuteAndTest(mem, lib, v, output) + } } class Masks_PowersOfTwo_64_1 @@ -181,7 +205,9 @@ class Masks_PowersOfTwo_64_1 override lazy val memMaskGran = Some(64) override lazy val libMaskGran = Some(1) - compileExecuteAndTest(mem, lib, v, output) + it should "compile, execute, and test" in { + compileExecuteAndTest(mem, lib, v, output) + } } // Simple powers of two with non bit-masked lib. @@ -195,7 +221,9 @@ class Masks_PowersOfTwo_32_4 override lazy val memMaskGran = Some(32) override lazy val libMaskGran = Some(4) - compileExecuteAndTest(mem, lib, v, output) + it should "compile, execute, and test" in { + compileExecuteAndTest(mem, lib, v, output) + } } class Masks_PowersOfTwo_32_8 @@ -207,7 +235,9 @@ class Masks_PowersOfTwo_32_8 override lazy val memMaskGran = Some(32) override lazy val libMaskGran = Some(8) - compileExecuteAndTest(mem, lib, v, output) + it should "compile, execute, and test" in { + compileExecuteAndTest(mem, lib, v, output) + } } class Masks_PowersOfTwo_8_8 @@ -219,7 +249,9 @@ class Masks_PowersOfTwo_8_8 override lazy val memMaskGran = Some(8) override lazy val libMaskGran = Some(8) - compileExecuteAndTest(mem, lib, v, output) + it should "compile, execute, and test" in { + compileExecuteAndTest(mem, lib, v, output) + } } // Width as a multiple of the mask, bit-masked lib @@ -233,7 +265,9 @@ class Masks_IntegerMaskMultiple_20_10 override lazy val memMaskGran = Some(10) override lazy val libMaskGran = Some(1) - compileExecuteAndTest(mem, lib, v, output) + it should "compile, execute, and test" in { + compileExecuteAndTest(mem, lib, v, output) + } } class Masks_IntegerMaskMultiple_21_7 @@ -258,7 +292,9 @@ class Masks_IntegerMaskMultiple_21_21 override lazy val memMaskGran = Some(21) override lazy val libMaskGran = Some(1) - compileExecuteAndTest(mem, lib, v, output) + it should "compile, execute, and test" in { + compileExecuteAndTest(mem, lib, v, output) + } } class Masks_IntegerMaskMultiple_84_21 @@ -270,7 +306,9 @@ class Masks_IntegerMaskMultiple_84_21 override lazy val memMaskGran = Some(21) override lazy val libMaskGran = Some(1) - compileExecuteAndTest(mem, lib, v, output) + it should "compile, execute, and test" in { + compileExecuteAndTest(mem, lib, v, output) + } } class Masks_IntegerMaskMultiple_92_23 @@ -282,7 +320,9 @@ class Masks_IntegerMaskMultiple_92_23 override lazy val memMaskGran = Some(23) override lazy val libMaskGran = Some(1) - compileExecuteAndTest(mem, lib, v, output) + it should "compile, execute, and test" in { + compileExecuteAndTest(mem, lib, v, output) + } } class Masks_IntegerMaskMultiple_117_13 @@ -294,7 +334,9 @@ class Masks_IntegerMaskMultiple_117_13 override lazy val memMaskGran = Some(13) override lazy val libMaskGran = Some(1) - compileExecuteAndTest(mem, lib, v, output) + it should "compile, execute, and test" in { + compileExecuteAndTest(mem, lib, v, output) + } } class Masks_IntegerMaskMultiple_160_20 @@ -306,7 +348,9 @@ class Masks_IntegerMaskMultiple_160_20 override lazy val memMaskGran = Some(20) override lazy val libMaskGran = Some(1) - compileExecuteAndTest(mem, lib, v, output) + it should "compile, execute, and test" in { + compileExecuteAndTest(mem, lib, v, output) + } } class Masks_IntegerMaskMultiple_184_23 @@ -318,7 +362,9 @@ class Masks_IntegerMaskMultiple_184_23 override lazy val memMaskGran = Some(23) override lazy val libMaskGran = Some(1) - compileExecuteAndTest(mem, lib, v, output) + it should "compile, execute, and test" in { + compileExecuteAndTest(mem, lib, v, output) + } } // Width as an non-integer multiple of the mask, bit-masked lib diff --git a/tapeout/src/test/scala/barstools/macros/SpecificExamples.scala b/tapeout/src/test/scala/barstools/macros/SpecificExamples.scala index 6ee7255a..1a957199 100644 --- a/tapeout/src/test/scala/barstools/macros/SpecificExamples.scala +++ b/tapeout/src/test/scala/barstools/macros/SpecificExamples.scala @@ -27,7 +27,7 @@ class WriteEnableTest extends MacroCompilerSpec with HasSRAMGenerator { val lib = s"lib-WriteEnableTest.json" // lib. of mems to create it val v = s"WriteEnableTest.json" - override val libPrefix = "tapeout/src/test/resources" + override val libPrefix = "src/test/resources" val memSRAMs = mdf.macrolib.Utils .readMDFFromString(""" @@ -89,7 +89,9 @@ circuit cc_banks_0_ext : defname = fake_mem """ - compileExecuteAndTest(mem, lib, v, output) + it should "compile, execute, and test" in { + compileExecuteAndTest(mem, lib, v, output) + } } class MaskPortTest extends MacroCompilerSpec with HasSRAMGenerator { @@ -97,7 +99,7 @@ class MaskPortTest extends MacroCompilerSpec with HasSRAMGenerator { val lib = s"lib-MaskPortTest.json" // lib. of mems to create it val v = s"MaskPortTest.json" - override val libPrefix = "tapeout/src/test/resources" + override val libPrefix = "src/test/resources" val memSRAMs = mdf.macrolib.Utils .readMDFFromString(""" @@ -173,7 +175,9 @@ circuit cc_dir_ext : defname = fake_mem """ - compileExecuteAndTest(mem, lib, v, output) + it should "compile, exectue, and test" in { + compileExecuteAndTest(mem, lib, v, output) + } } class BOOMTest extends MacroCompilerSpec with HasSRAMGenerator { @@ -181,10 +185,9 @@ class BOOMTest extends MacroCompilerSpec with HasSRAMGenerator { val lib = s"lib-BOOMTest.json" val v = s"BOOMTest.v" - override val libPrefix = "tapeout/src/test/resources" + override val libPrefix = "src/test/resources" - val memSRAMs = mdf.macrolib.Utils - .readMDFFromString(""" + val memSRAMs = mdf.macrolib.Utils.readMDFFromString(""" [ { "type" : "sram", "name" : "_T_182_ext", @@ -1345,7 +1348,9 @@ circuit smem_0_ext : defname = my_sram_1rw_64x8 """ - compileExecuteAndTest(mem, lib, v, output) + it should "compile, execute and test the boom test" in { + compileExecuteAndTest(mem, lib, v, output) + } } class SmallTagArrayTest extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleTestGenerator { @@ -1378,7 +1383,9 @@ class SmallTagArrayTest extends MacroCompilerSpec with HasSRAMGenerator with Has | dout <= mux(UInt<1>("h1"), dout_0, UInt<26>("h0")) """.stripMargin - compileExecuteAndTest(mem, lib, v, output) + it should "compile, execute, and test, the small tag array test" in { + compileExecuteAndTest(mem, lib, v, output) + } } class RocketChipTest extends MacroCompilerSpec with HasSRAMGenerator { diff --git a/tapeout/src/test/scala/barstools/tapeout/transforms/GenerateSpec.scala b/tapeout/src/test/scala/barstools/tapeout/transforms/GenerateSpec.scala index ec4822fe..5c7d53f1 100644 --- a/tapeout/src/test/scala/barstools/tapeout/transforms/GenerateSpec.scala +++ b/tapeout/src/test/scala/barstools/tapeout/transforms/GenerateSpec.scala @@ -7,6 +7,9 @@ import chisel3.experimental.ExtModule import chisel3.stage.ChiselStage import firrtl.FileUtils import org.scalatest.freespec.AnyFreeSpec +import org.scalatest.matchers.must.Matchers.be +import org.scalatest.matchers.should.Matchers +import org.scalatest.matchers.should.Matchers.convertToAnyShouldWrapper import java.io.{File, PrintWriter} @@ -61,9 +64,7 @@ class GenerateSpec extends AnyFreeSpec { val targetDir = "test_run_dir/generate_spec_source" FileUtils.makeDirectory(targetDir) - val printWriter = new PrintWriter(new File(s"$targetDir/GenerateExampleTester.fir")) - printWriter.write((new ChiselStage()).emitFirrtl(new GenerateExampleTester, Array("--target-dir", targetDir))) - printWriter.close() + (new ChiselStage()).emitFirrtl(new GenerateExampleTester, Array("--target-dir", targetDir)) val blackBoxInverterText = """ |module BlackBoxInverter( @@ -78,7 +79,7 @@ class GenerateSpec extends AnyFreeSpec { printWriter2.write(blackBoxInverterText) printWriter2.close() - + new File(s"$targetDir/GenerateExampleTester.fir").exists() should be (true) } "generate top test" in { @@ -89,5 +90,6 @@ class GenerateSpec extends AnyFreeSpec { "-i", s"$sourceDir/GenerateExampleTester.fir", "-o", s"$targetDir/GenerateExampleTester.v" )) + new File(s"$targetDir/GenerateExampleTester.v").exists() should be (true) } } diff --git a/tapeout/src/test/scala/barstools/tapeout/transforms/GenerateTopSpec.scala b/tapeout/src/test/scala/barstools/tapeout/transforms/GenerateTopSpec.scala index 02afa79a..e4824c4c 100644 --- a/tapeout/src/test/scala/barstools/tapeout/transforms/GenerateTopSpec.scala +++ b/tapeout/src/test/scala/barstools/tapeout/transforms/GenerateTopSpec.scala @@ -27,8 +27,7 @@ class GenerateTopSpec extends AnyFreeSpec with Matchers { val targetDir = "test_run_dir/generate_top_spec" FileUtils.makeDirectory(targetDir) - val stream = getClass.getResourceAsStream("/BlackBoxFloatTester.fir") - val input = scala.io.Source.fromInputStream(stream).getLines() + val input = FileUtils.getLinesResource("/BlackBoxFloatTester.fir") val printWriter = new PrintWriter(new File(s"$targetDir/BlackBoxFloatTester.fir")) printWriter.write(input.mkString("\n")) printWriter.close() diff --git a/tapeout/src/test/scala/mdf/macrolib/FlipChipMacroSpec.scala b/tapeout/src/test/scala/mdf/macrolib/FlipChipMacroSpec.scala index ba51e4d1..c6a9e7ce 100644 --- a/tapeout/src/test/scala/mdf/macrolib/FlipChipMacroSpec.scala +++ b/tapeout/src/test/scala/mdf/macrolib/FlipChipMacroSpec.scala @@ -1,12 +1,13 @@ package mdf.macrolib +import firrtl.FileUtils import org.scalatest.flatspec.AnyFlatSpec import org.scalatest.matchers.should.Matchers class FlipChipMacroSpec extends AnyFlatSpec with Matchers { "Parsing flipchipmacros" should "work" in { - val stream = getClass.getResourceAsStream("/bumps.json") - val mdf = Utils.readMDFFromString(scala.io.Source.fromInputStream(stream).getLines().mkString("\n")) + val stream = FileUtils.getLinesResource("/bumps.json") + val mdf = Utils.readMDFFromString(stream.mkString("\n")) mdf match { case Some(Seq(fcp: FlipChipMacro)) => println(fcp.visualize) } diff --git a/tapeout/src/test/scala/mdf/macrolib/IOPropertiesSpec.scala b/tapeout/src/test/scala/mdf/macrolib/IOPropertiesSpec.scala index ffd13be5..b09422a7 100644 --- a/tapeout/src/test/scala/mdf/macrolib/IOPropertiesSpec.scala +++ b/tapeout/src/test/scala/mdf/macrolib/IOPropertiesSpec.scala @@ -1,12 +1,13 @@ package mdf.macrolib +import firrtl.FileUtils import org.scalatest.flatspec.AnyFlatSpec import org.scalatest.matchers.should.Matchers class IOPropertiesSpec extends AnyFlatSpec with Matchers { "Parsing io_properties" should "work" in { - val stream = getClass.getResourceAsStream("/io_properties.json") - val mdf = Utils.readMDFFromString(scala.io.Source.fromInputStream(stream).getLines().mkString("\n")) + val stream = FileUtils.getLinesResource("/io_properties.json") + val mdf = Utils.readMDFFromString(stream.mkString("\n")) mdf match { case Some(Seq(fcp: IOProperties)) => }