wu-arch/chipyard
1
0
Fork 0
Code Issues Pull Requests Actions 1 Packages Projects Releases Wiki Activity

Bumps barstools and fixes build system after (#63)

Browse Source 
Barstools now handles annotations correctly.
This means that the blackboxresources for the harness
and top are different and need to be merged in the build system.
We also add all Sim*.cc files to default resources as our new emulator
demands. We then remove them from the harness .f file to avoid having
to detect which ones to include selectively.
This commit is contained in:
Colin Schmidt
2019-03-28 11:47:32 -07:00
committed by GitHub
parent cf9136de4a
commit 3425def36b
5 changed files with 10 additions and 10 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
Makefrag
View File

@@ -34,6 +34,8 @@ HARNESS_FILE ?=$(build_dir)/$(long_name).harness.v
SMEMS_FILE ?=$(build_dir)/$(long_name).mems.v SMEMS_FILE ?=$(build_dir)/$(long_name).mems.v
SMEMS_CONF ?=$(build_dir)/$(long_name).mems.conf SMEMS_CONF ?=$(build_dir)/$(long_name).mems.conf
sim_dotf ?= $(build_dir)/sim_files.f sim_dotf ?= $(build_dir)/sim_files.f
sim_harness_blackboxes ?= $(build_dir)/firrtl_black_box_resource_files.harness.f
sim_top_blackboxes ?= $(build_dir)/firrtl_black_box_resource_files.top.f
REPL_SEQ_MEM = --infer-rw --repl-seq-mem -c:$(MODEL):-o:$(SMEMS_CONF) REPL_SEQ_MEM = --infer-rw --repl-seq-mem -c:$(MODEL):-o:$(SMEMS_CONF)
@@ -63,9 +65,11 @@ $(FIRRTL_FILE) $(ANNO_FILE): $(SCALA_SOURCES) $(sim_dotf)
$(VERILOG_FILE) $(SMEMS_CONF): $(FIRRTL_FILE) $(ANNO_FILE) $(TAPEOUT_JAR) $(VERILOG_FILE) $(SMEMS_CONF): $(FIRRTL_FILE) $(ANNO_FILE) $(TAPEOUT_JAR)
$(TAPEOUT) barstools.tapeout.transforms.GenerateTop -o $(VERILOG_FILE) -i $(FIRRTL_FILE) --syn-top $(TOP) --harness-top $(MODEL) -faf $(ANNO_FILE) $(REPL_SEQ_MEM) -td $(build_dir) $(TAPEOUT) barstools.tapeout.transforms.GenerateTop -o $(VERILOG_FILE) -i $(FIRRTL_FILE) --syn-top $(TOP) --harness-top $(MODEL) -faf $(ANNO_FILE) $(REPL_SEQ_MEM) -td $(build_dir)
cp $(build_dir)/firrtl_black_box_resource_files.f $(sim_top_blackboxes)
$(HARNESS_FILE): $(FIRRTL_FILE) $(ANNO_FILE) $(TAPEOUT_JAR) $(HARNESS_FILE): $(FIRRTL_FILE) $(ANNO_FILE) $(TAPEOUT_JAR) $(sim_top_blackboxes)
$(TAPEOUT) barstools.tapeout.transforms.GenerateHarness -o $(HARNESS_FILE) -i $(FIRRTL_FILE) --syn-top $(TOP) --harness-top $(MODEL) -faf $(ANNO_FILE) -td $(build_dir) $(TAPEOUT) barstools.tapeout.transforms.GenerateHarness -o $(HARNESS_FILE) -i $(FIRRTL_FILE) --syn-top $(TOP) --harness-top $(MODEL) -faf $(ANNO_FILE) -td $(build_dir)
grep -v "SimSerial.cc\|SimDTM.cc\|SimJTAG.cc" $(build_dir)/firrtl_black_box_resource_files.f > $(sim_harness_blackboxes)
# This file is for simulation only. VLSI flows should replace this file with one containing hard SRAMs # This file is for simulation only. VLSI flows should replace this file with one containing hard SRAMs
$(SMEMS_FILE): $(SMEMS_CONF) $(MACROCOMPILER_JAR) $(SMEMS_FILE): $(SMEMS_CONF) $(MACROCOMPILER_JAR)

2
barstools

Submodule barstools updated: 0b9d74ada7...8f7af5b0bf

1
src/main/scala/example/Simulator.scala
View File

@@ -82,6 +82,7 @@ object GenerateSimFiles extends App with HasGenerateSimConfig {
out.close() out.close()
} }
def resources(sim: Simulator): Seq[String] = Seq( def resources(sim: Simulator): Seq[String] = Seq(
"/testchipip/csrc/SimSerial.cc",
"/csrc/SimDTM.cc", "/csrc/SimDTM.cc",
"/csrc/SimJTAG.cc", "/csrc/SimJTAG.cc",
"/csrc/remote_bitbang.h", "/csrc/remote_bitbang.h",

7
verisim/Makefile
View File

@@ -26,9 +26,6 @@ ifneq ($(filter run% %.run %.out %.vpd %.vcd,$(MAKECMDGOALS)),)
-include $(build_dir)/$(long_name).d -include $(build_dir)/$(long_name).d
endif endif
sim_blackboxes = \
$(build_dir)/firrtl_black_box_resource_files.f
rocketchip_vsrc_dir = $(ROCKETCHIP_DIR)/src/main/resources/vsrc rocketchip_vsrc_dir = $(ROCKETCHIP_DIR)/src/main/resources/vsrc
sim_vsrcs = \ sim_vsrcs = \
@@ -49,7 +46,7 @@ $(model_mk): $(sim_vsrcs) $(sim_dotf) $(INSTALLED_VERILATOR)
rm -rf $(build_dir)/$(long_name) rm -rf $(build_dir)/$(long_name)
mkdir -p $(build_dir)/$(long_name) mkdir -p $(build_dir)/$(long_name)
$(VERILATOR) $(VERILATOR_FLAGS) -Mdir $(build_dir)/$(long_name) \ $(VERILATOR) $(VERILATOR_FLAGS) -Mdir $(build_dir)/$(long_name) \
-o $(sim) $(sim_vsrcs) -f $(sim_dotf) -f $(sim_blackboxes) -LDFLAGS "$(LDFLAGS)" \ -o $(sim) $(sim_vsrcs) -f $(sim_dotf) -f $(sim_top_blackboxes) -f $(sim_harness_blackboxes) -LDFLAGS "$(LDFLAGS)" \
-CFLAGS "-I$(build_dir) -include $(build_dir)/$(long_name).plusArgs -include $(model_header)" -CFLAGS "-I$(build_dir) -include $(build_dir)/$(long_name).plusArgs -include $(model_header)"
touch $@ touch $@
@@ -61,7 +58,7 @@ $(model_mk_debug): $(sim_vsrcs) $(sim_dotf) $(INSTALLED_VERILATOR)
rm -rf $(build_dir)/$(long_name) rm -rf $(build_dir)/$(long_name)
mkdir -p $(build_dir)/$(long_name).debug mkdir -p $(build_dir)/$(long_name).debug
$(VERILATOR) $(VERILATOR_FLAGS) -Mdir $(build_dir)/$(long_name).debug --trace \ $(VERILATOR) $(VERILATOR_FLAGS) -Mdir $(build_dir)/$(long_name).debug --trace \
-o $(sim_debug) $(sim_vsrcs) -f $(sim_dotf) -f $(sim_blackboxes) -LDFLAGS "$(LDFLAGS)" \ -o $(sim_debug) $(sim_vsrcs) -f $(sim_dotf) -f $(sim_top_blackboxes) -f $(sim_harness_blackboxes) -LDFLAGS "$(LDFLAGS)" \
-CFLAGS "-I$(build_dir) -include $(build_dir)/$(long_name).plusArgs -include $(model_header_debug)" -CFLAGS "-I$(build_dir) -include $(build_dir)/$(long_name).plusArgs -include $(model_header_debug)"
touch $@ touch $@

4
vsim/Makefile
View File

@@ -22,8 +22,6 @@ ifneq ($(filter run% %.run %.out %.vpd %.vcd,$(MAKECMDGOALS)),)
-include $(build_dir)/$(long_name).d -include $(build_dir)/$(long_name).d
endif endif
sim_blackboxes = \
$(build_dir)/firrtl_black_box_resource_files.f
rocketchip_vsrc_dir = $(ROCKETCHIP_DIR)/src/main/resources/vsrc rocketchip_vsrc_dir = $(ROCKETCHIP_DIR)/src/main/resources/vsrc
@@ -40,7 +38,7 @@ VCS_OPTS = -notice -line +lint=all,noVCDE,noONGS,noUI -error=PCWM-L -timescale=1
-CC "-I$(RISCV)/include" \ -CC "-I$(RISCV)/include" \
-CC "-std=c++11" \ -CC "-std=c++11" \
-CC "-Wl,-rpath,$(RISCV)/lib" \ -CC "-Wl,-rpath,$(RISCV)/lib" \
-f $(sim_blackboxes) -f $(sim_dotf) \ -f $(sim_top_blackboxes) -f $(sim_harness_blackboxes) -f $(sim_dotf) \
$(RISCV)/lib/libfesvr.so \ $(RISCV)/lib/libfesvr.so \
-sverilog \ -sverilog \
+incdir+$(generated_dir) \ +incdir+$(generated_dir) \