Move barstools tapeout src to tools/tapeout
This commit is contained in:
Jerry Zhao
152
tools/tapeout/src/main/scala/macros/SynFlopsPass.scala
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152
tools/tapeout/src/main/scala/macros/SynFlopsPass.scala
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// See LICENSE for license details.
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package barstools.macros
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import barstools.macros.Utils._
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import firrtl.Utils.{one, zero}
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import firrtl._
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import firrtl.ir._
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import firrtl.passes.MemPortUtils.memPortField
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import scala.collection.mutable
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class SynFlopsPass(synflops: Boolean, libs: Seq[Macro]) extends firrtl.passes.Pass {
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val extraMods: mutable.ArrayBuffer[Module] = scala.collection.mutable.ArrayBuffer.empty[Module]
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lazy val libMods: Map[String, Module] = libs.map { lib =>
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lib.src.name -> {
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val (dataType, dataWidth) = lib.src.ports.foldLeft(None: Option[BigInt])((res, port) =>
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(res, port.maskPort) match {
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case (_, None) =>
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res
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case (None, Some(_)) =>
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Some(port.effectiveMaskGran)
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case (Some(x), Some(_)) =>
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assert(x == port.effectiveMaskGran)
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res
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}
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) match {
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case None => (UIntType(IntWidth(lib.src.width)), lib.src.width)
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case Some(gran) => (UIntType(IntWidth(gran)), gran.intValue)
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}
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val maxDepth = firrtl.Utils.min(lib.src.depth, 1 << 26)
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// Change macro to be mapped onto to look like the below mem
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// by changing its depth, and width
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val lib_macro = new Macro(
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lib.src.copy(
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name = "split_" + lib.src.name,
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depth = maxDepth,
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width = dataWidth,
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ports = lib.src.ports.map(p =>
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p.copy(
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width = p.width.map(_ => dataWidth),
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depth = p.depth.map(_ => maxDepth),
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maskGran = p.maskGran.map(_ => dataWidth)
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)
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)
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)
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)
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val mod_macro = new MacroCompilerPass(None, None, None, None).compile(lib, lib_macro)
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val (real_mod, real_macro) = mod_macro.get
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val mem = DefMemory(
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NoInfo,
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"ram",
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dataType,
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maxDepth,
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1, // writeLatency
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1, // readLatency. This is possible because of VerilogMemDelays
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real_macro.readers.indices.map(i => s"R_$i"),
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real_macro.writers.indices.map(i => s"W_$i"),
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real_macro.readwriters.indices.map(i => s"RW_$i")
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)
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val readConnects = real_macro.readers.zipWithIndex.flatMap { case (r, i) =>
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val clock = portToExpression(r.src.clock.get)
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val address = portToExpression(r.src.address)
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val enable = (r.src.chipEnable, r.src.readEnable) match {
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case (Some(en_port), Some(re_port)) =>
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and(portToExpression(en_port), portToExpression(re_port))
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case (Some(en_port), None) => portToExpression(en_port)
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case (None, Some(re_port)) => portToExpression(re_port)
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case (None, None) => one
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}
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val data = memPortField(mem, s"R_$i", "data")
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val read = data
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Seq(
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Connect(NoInfo, memPortField(mem, s"R_$i", "clk"), clock),
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Connect(NoInfo, memPortField(mem, s"R_$i", "addr"), address),
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Connect(NoInfo, memPortField(mem, s"R_$i", "en"), enable),
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Connect(NoInfo, WRef(r.src.output.get.name), read)
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)
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}
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val writeConnects = real_macro.writers.zipWithIndex.flatMap { case (w, i) =>
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val clock = portToExpression(w.src.clock.get)
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val address = portToExpression(w.src.address)
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val enable = (w.src.chipEnable, w.src.writeEnable) match {
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case (Some(en), Some(we)) =>
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and(portToExpression(en), portToExpression(we))
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case (Some(en), None) => portToExpression(en)
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case (None, Some(we)) => portToExpression(we)
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case (None, None) => zero // is it possible?
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}
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val mask = w.src.maskPort match {
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case Some(m) => portToExpression(m)
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case None => one
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}
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val data = memPortField(mem, s"W_$i", "data")
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val write = portToExpression(w.src.input.get)
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Seq(
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Connect(NoInfo, memPortField(mem, s"W_$i", "clk"), clock),
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Connect(NoInfo, memPortField(mem, s"W_$i", "addr"), address),
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Connect(NoInfo, memPortField(mem, s"W_$i", "en"), enable),
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Connect(NoInfo, memPortField(mem, s"W_$i", "mask"), mask),
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Connect(NoInfo, data, write)
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)
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}
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val readwriteConnects = real_macro.readwriters.zipWithIndex.flatMap { case (rw, i) =>
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val clock = portToExpression(rw.src.clock.get)
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val address = portToExpression(rw.src.address)
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val wmode = rw.src.writeEnable match {
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case Some(we) => portToExpression(we)
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case None => zero // is it possible?
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}
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val wmask = rw.src.maskPort match {
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case Some(wm) => portToExpression(wm)
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case None => one
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}
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val enable = (rw.src.chipEnable, rw.src.readEnable) match {
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case (Some(en), Some(re)) =>
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and(portToExpression(en), or(portToExpression(re), wmode))
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case (Some(en), None) => portToExpression(en)
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case (None, Some(re)) => or(portToExpression(re), wmode)
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case (None, None) => one
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}
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val wdata = memPortField(mem, s"RW_$i", "wdata")
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val rdata = memPortField(mem, s"RW_$i", "rdata")
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val write = portToExpression(rw.src.input.get)
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val read = rdata
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Seq(
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Connect(NoInfo, memPortField(mem, s"RW_$i", "clk"), clock),
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Connect(NoInfo, memPortField(mem, s"RW_$i", "addr"), address),
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Connect(NoInfo, memPortField(mem, s"RW_$i", "en"), enable),
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Connect(NoInfo, memPortField(mem, s"RW_$i", "wmode"), wmode),
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Connect(NoInfo, memPortField(mem, s"RW_$i", "wmask"), wmask),
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Connect(NoInfo, WRef(rw.src.output.get.name), read),
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Connect(NoInfo, wdata, write)
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)
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}
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extraMods.append(real_macro.module(Block(mem +: (readConnects ++ writeConnects ++ readwriteConnects))))
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real_mod
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}
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}.toMap
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def run(c: Circuit): Circuit = {
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if (!synflops) c
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else c.copy(modules = c.modules.map(m => libMods.getOrElse(m.name, m)) ++ extraMods)
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}
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}
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