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Fix FireChip MultiCycleRegfileImp mixin

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This commit is contained in:
Jerry Zhao
2019-10-07 13:24:23 -07:00
parent 4cba46c4e0
commit 331a2a6dda
1 changed files with 20 additions and 15 deletions
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35
generators/firechip/src/main/scala/TargetMixins.scala
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@@ -8,6 +8,7 @@ import freechips.rocketchip.tilelink._
import freechips.rocketchip.subsystem._ import freechips.rocketchip.subsystem._
import freechips.rocketchip.amba.axi4._ import freechips.rocketchip.amba.axi4._
import freechips.rocketchip.util._ import freechips.rocketchip.util._
import freechips.rocketchip.tile._
import freechips.rocketchip.subsystem._ import freechips.rocketchip.subsystem._
import freechips.rocketchip.rocket.TracedInstruction import freechips.rocketchip.rocket.TracedInstruction
import firesim.endpoints.{TraceOutputTop, DeclockedTracedInstruction} import firesim.endpoints.{TraceOutputTop, DeclockedTracedInstruction}
@@ -15,6 +16,8 @@ import firesim.endpoints.{TraceOutputTop, DeclockedTracedInstruction}
import midas.models.AXI4BundleWithEdge import midas.models.AXI4BundleWithEdge
import midas.targetutils.{ExcludeInstanceAsserts, MemModelAnnotation} import midas.targetutils.{ExcludeInstanceAsserts, MemModelAnnotation}
import boom.common.BoomTile
/** Copied from RC and modified to change the IO type of the Imp to include the Diplomatic edges /** Copied from RC and modified to change the IO type of the Imp to include the Diplomatic edges
* associated with each port. This drives FASED functional model sizing * associated with each port. This drives FASED functional model sizing
*/ */
@@ -107,21 +110,23 @@ trait ExcludeInvalidBoomAssertions extends LazyModuleImp {
trait CanHaveMultiCycleRegfileImp { trait CanHaveMultiCycleRegfileImp {
val outer: utilities.HasBoomAndRocketTiles val outer: utilities.HasBoomAndRocketTiles
val boomCores = outer.boomTiles.map(tile => tile.module.core)
boomCores.foreach({ core =>
core.iregfile match {
case irf: boom.exu.RegisterFileSynthesizable => annotate(MemModelAnnotation(irf.regfile))
case _ => Nil
}
if (core.fp_pipeline != null) core.fp_pipeline.fregfile match { outer.tiles.map {
case irf: boom.exu.RegisterFileSynthesizable => annotate(MemModelAnnotation(irf.regfile)) case r: RocketTile => {
case _ => Nil annotate(MemModelAnnotation(r.module.core.rocketImpl.rf.rf))
r.module.fpuOpt.foreach(fpu => annotate(MemModelAnnotation(fpu.fpuImpl.regfile)))
} }
}) case b: BoomTile => {
val core = b.module.core
outer.rocketTiles.foreach({ tile => core.iregfile match {
annotate(MemModelAnnotation(tile.module.core.rocketImpl.rf.rf)) case irf: boom.exu.RegisterFileSynthesizable => annotate(MemModelAnnotation(irf.regfile))
tile.module.fpuOpt.foreach(fpu => annotate(MemModelAnnotation(fpu.fpuImpl.regfile))) case _ => Nil
}) }
if (core.fp_pipeline != null) core.fp_pipeline.fregfile match {
case frf: boom.exu.RegisterFileSynthesizable => annotate(MemModelAnnotation(frf.regfile))
case _ => Nil
}
}
}
} }