From 3196d44f224d7dd3df951e5467c7e3ffcca2253d Mon Sep 17 00:00:00 2001 From: "-T.K.-" Date: Thu, 20 Apr 2023 13:55:23 -0700 Subject: [PATCH] FIX: fix wording in doc We don't require the host computer to be x86 (can be RISC-V!) --- docs/Advanced-Concepts/Chip-Communication.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/Advanced-Concepts/Chip-Communication.rst b/docs/Advanced-Concepts/Chip-Communication.rst index 1dc5ff45..f43ad628 100644 --- a/docs/Advanced-Concepts/Chip-Communication.rst +++ b/docs/Advanced-Concepts/Chip-Communication.rst @@ -211,7 +211,7 @@ Softcore-driven Bringup Setup of the Example Test Chip after Tapeout .. warning:: Bringing up test chips with a FPGA softcore as described here is discouraged. - An alternative approach using the FPGA to "bridge" between a x86 host and the test chip is the preferred approach. + An alternative approach using the FPGA to "bridge" between a host computer and the test chip is the preferred approach. Assuming this example test chip is taped out and now ready to be tested, we can communicate with the chip using this serial-link. For example, a common test setup used at Berkeley to evaluate Chipyard-based test-chips includes an FPGA running a RISC-V soft-core that is able to speak to the DUT (over an FMC).