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readme addition | pipe out output | renamed output files

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abejgonzalez
2019-05-20 17:12:22 -07:00
parent 65d6a900c3
commit 30d54a6851
5 changed files with 15 additions and 4 deletions
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2
common.mk
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@@ -71,7 +71,7 @@ verilog: $(sim_vsrcs)
# helper rules to run simulator
#########################################################################################
run-binary: $(sim)
$(sim) $(PERMISSIVEON) $(SIM_FLAGS) $(PERMISSIVEOFF) $(BINARY)
$(sim) $(PERMISSIVEON) $(SIM_FLAGS) $(PERMISSIVEOFF) $(BINARY) 3>&1 1>&2 2>&3 | spike-dasm > $(sim_out_name).out
#########################################################################################
# run assembly/benchmarks rules