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readme addition | pipe out output | renamed output files

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abejgonzalez
2019-05-20 17:12:22 -07:00
parent 65d6a900c3
commit 30d54a6851
5 changed files with 15 additions and 4 deletions
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README.md
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@@ -50,6 +50,16 @@ build an alternate configuration.
make PROJECT=yourproject CONFIG=YourConfig
./simulator-yourproject-YourConfig ...
Additionally, you can use a helper make rule to run your simulation binary. The output will be in the "verisim"
directory under the file names: `<binary-name>.<type of project/config/etc it ran on>.*`
# first make your verisim rtl simulator binary
make SUB_PROJECT=example
# then run the binary (with no vcd generation)
make SUB_PROJECT=example BINARY=<my-riscv-binary> run-binary
# then run the binary (with vcd generation)
make SUB_PROJECT=example BINARY=<my-riscv-binary> run-binary-debug
## Submodules and Subdirectories
The submodules and subdirectories for the project template are organized as