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More clarifications on harness clocks

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This commit is contained in:
Abraham Gonzalez
2021-03-11 03:54:56 +00:00
parent 1ebc0f7a7e
commit 30c9b63e7b
2 changed files with 29 additions and 10 deletions
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3
generators/chipyard/src/main/scala/HarnessBinders.scala
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@@ -158,10 +158,11 @@ class WithSimAXIMemOverSerialTL extends OverrideHarnessBinder({
ports.map({ port =>
// DOC include start: HarnessClockInstantiatorEx
val memOverSerialTLClockBundle = p(HarnessClockInstantiatorKey).getClockBundle("mem_over_serial_tl_clock", memFreq)
val harnessMultiClockAXIRAM = SerialAdapter.connectHarnessMultiClockAXIRAM(
system.serdesser.get,
port,
p(HarnessClockInstantiatorKey).getClockBundle("mem_over_serial_tl_clock", memFreq),
memOverSerialTLClockBundle,
th.harnessReset)
// DOC include end: HarnessClockInstantiatorEx
val success = SerialAdapter.connectSimSerial(harnessMultiClockAXIRAM.module.io.tsi_ser, port.clock, th.harnessReset.asBool)