From c60d0475b64f7fa6822dd5b476572c4afa5ce7f6 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Thu, 16 May 2024 09:46:06 -0700 Subject: [PATCH 1/4] remove redundant CLASSPATH_TARGETS (this is always the same as CLASSPATH) --- common.mk | 10 +++++----- variables.mk | 3 --- 2 files changed, 5 insertions(+), 8 deletions(-) diff --git a/common.mk b/common.mk index a0f3e6ac..8aa41ca7 100644 --- a/common.mk +++ b/common.mk @@ -119,13 +119,13 @@ $(BOOTROM_TARGETS): $(build_dir)/bootrom.%.img: $(TESTCHIP_RSRCS_DIR)/testchipip ######################################################################################### # compile scala jars ######################################################################################### -$(CHIPYARD_CLASSPATH_TARGETS) &: $(CHIPYARD_SCALA_SOURCES) $(SCALA_BUILDTOOL_DEPS) $(CHIPYARD_VLOG_SOURCES) +$(CHIPYARD_CLASSPATH) &: $(CHIPYARD_SCALA_SOURCES) $(SCALA_BUILDTOOL_DEPS) $(CHIPYARD_VLOG_SOURCES) $(CHECK_SUBMODULES_COMMAND) mkdir -p $(dir $@) $(call run_sbt_assembly,$(SBT_PROJECT),$(CHIPYARD_CLASSPATH)) # order only dependency between sbt runs needed to avoid concurrent sbt runs -$(TAPEOUT_CLASSPATH_TARGETS) &: $(TAPEOUT_SCALA_SOURCES) $(SCALA_BUILDTOOL_DEPS) $(TAPEOUT_VLOG_SOURCES) | $(CHIPYARD_CLASSPATH_TARGETS) +$(TAPEOUT_CLASSPATH) &: $(TAPEOUT_SCALA_SOURCES) $(SCALA_BUILDTOOL_DEPS) $(TAPEOUT_VLOG_SOURCES) | $(CHIPYARD_CLASSPATH) mkdir -p $(dir $@) $(call run_sbt_assembly,tapeout,$(TAPEOUT_CLASSPATH)) @@ -133,7 +133,7 @@ $(TAPEOUT_CLASSPATH_TARGETS) &: $(TAPEOUT_SCALA_SOURCES) $(SCALA_BUILDTOOL_DEPS) # verilog generation pipeline ######################################################################################### # AG: must re-elaborate if cva6 sources have changed... otherwise just run firrtl compile -$(FIRRTL_FILE) $(ANNO_FILE) $(CHISEL_LOG_FILE) &: $(CHIPYARD_CLASSPATH_TARGETS) $(EXTRA_GENERATOR_REQS) +$(FIRRTL_FILE) $(ANNO_FILE) $(CHISEL_LOG_FILE) &: $(CHIPYARD_CLASSPATH) $(EXTRA_GENERATOR_REQS) mkdir -p $(build_dir) (set -o pipefail && $(call run_jar_scala_main,$(CHIPYARD_CLASSPATH),$(GENERATOR_PACKAGE).Generator,\ --target-dir $(build_dir) \ @@ -242,12 +242,12 @@ $(TOP_SMEMS_CONF) $(MODEL_SMEMS_CONF) &: $(MFC_SMEMS_CONF) $(MFC_MODEL_HRCHY_JS # This file is for simulation only. VLSI flows should replace this file with one containing hard SRAMs TOP_MACROCOMPILER_MODE ?= --mode synflops -$(TOP_SMEMS_FILE) $(TOP_SMEMS_FIR) &: $(TAPEOUT_CLASSPATH_TARGETS) $(TOP_SMEMS_CONF) +$(TOP_SMEMS_FILE) $(TOP_SMEMS_FIR) &: $(TAPEOUT_CLASSPATH) $(TOP_SMEMS_CONF) $(call run_jar_scala_main,$(TAPEOUT_CLASSPATH),tapeout.macros.MacroCompiler,-n $(TOP_SMEMS_CONF) -v $(TOP_SMEMS_FILE) -f $(TOP_SMEMS_FIR) $(TOP_MACROCOMPILER_MODE)) touch $(TOP_SMEMS_FILE) $(TOP_SMEMS_FIR) MODEL_MACROCOMPILER_MODE = --mode synflops -$(MODEL_SMEMS_FILE) $(MODEL_SMEMS_FIR) &: $(TAPEOUT_CLASSPATH_TARGETS) $(MODEL_SMEMS_CONF) +$(MODEL_SMEMS_FILE) $(MODEL_SMEMS_FIR) &: $(TAPEOUT_CLASSPATH) $(MODEL_SMEMS_CONF) $(call run_jar_scala_main,$(TAPEOUT_CLASSPATH),tapeout.macros.MacroCompiler, -n $(MODEL_SMEMS_CONF) -v $(MODEL_SMEMS_FILE) -f $(MODEL_SMEMS_FIR) $(MODEL_MACROCOMPILER_MODE)) touch $(MODEL_SMEMS_FILE) $(MODEL_SMEMS_FIR) diff --git a/variables.mk b/variables.mk index 58cc85c4..e58e7f73 100644 --- a/variables.mk +++ b/variables.mk @@ -162,9 +162,6 @@ endif CLASSPATH_CACHE ?= $(base_dir)/.classpath_cache CHIPYARD_CLASSPATH ?= $(CLASSPATH_CACHE)/chipyard.jar TAPEOUT_CLASSPATH ?= $(CLASSPATH_CACHE)/tapeout.jar -# if *_CLASSPATH is a true java classpath, it can be colon-delimited list of paths (on *nix) -CHIPYARD_CLASSPATH_TARGETS ?= $(subst :, ,$(CHIPYARD_CLASSPATH)) -TAPEOUT_CLASSPATH_TARGETS ?= $(subst :, ,$(TAPEOUT_CLASSPATH)) # chisel generated outputs FIRRTL_FILE ?= $(build_dir)/$(long_name).fir From 9737d62635bd24208d3049f56b8a3b5946b76531 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Thu, 16 May 2024 09:50:36 -0700 Subject: [PATCH 2/4] Add comments on what CHIPYARD_CLASSPATH and TAPEOUT_CLASSPATH contain --- variables.mk | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/variables.mk b/variables.mk index e58e7f73..9c7d159a 100644 --- a/variables.mk +++ b/variables.mk @@ -160,7 +160,9 @@ endif # classpaths CLASSPATH_CACHE ?= $(base_dir)/.classpath_cache -CHIPYARD_CLASSPATH ?= $(CLASSPATH_CACHE)/chipyard.jar +# The chipyard classpath must contain the Generator main +CHIPYARD_CLASSPATH ?= $(CLASSPATH_CACHE)/$(SBT_PROJECT).jar +# The tapeout classpath must contain MacroCompiler TAPEOUT_CLASSPATH ?= $(CLASSPATH_CACHE)/tapeout.jar # chisel generated outputs From 0c3ede15af603c2e6a6e5e3a777a206a6cc04546 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Thu, 16 May 2024 09:51:40 -0700 Subject: [PATCH 3/4] Rename CHIPYARD_CLASSPATH to GENERATOR_CLASSPATH This name better reflects that this classpath must contain a Generator main, but does not have to necessarily be the chipyard project in build.sbt --- common.mk | 10 +++++----- variables.mk | 4 ++-- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/common.mk b/common.mk index 8aa41ca7..04d1374e 100644 --- a/common.mk +++ b/common.mk @@ -119,13 +119,13 @@ $(BOOTROM_TARGETS): $(build_dir)/bootrom.%.img: $(TESTCHIP_RSRCS_DIR)/testchipip ######################################################################################### # compile scala jars ######################################################################################### -$(CHIPYARD_CLASSPATH) &: $(CHIPYARD_SCALA_SOURCES) $(SCALA_BUILDTOOL_DEPS) $(CHIPYARD_VLOG_SOURCES) +$(GENERATOR_CLASSPATH) &: $(CHIPYARD_SCALA_SOURCES) $(SCALA_BUILDTOOL_DEPS) $(CHIPYARD_VLOG_SOURCES) $(CHECK_SUBMODULES_COMMAND) mkdir -p $(dir $@) - $(call run_sbt_assembly,$(SBT_PROJECT),$(CHIPYARD_CLASSPATH)) + $(call run_sbt_assembly,$(SBT_PROJECT),$(GENERATOR_CLASSPATH)) # order only dependency between sbt runs needed to avoid concurrent sbt runs -$(TAPEOUT_CLASSPATH) &: $(TAPEOUT_SCALA_SOURCES) $(SCALA_BUILDTOOL_DEPS) $(TAPEOUT_VLOG_SOURCES) | $(CHIPYARD_CLASSPATH) +$(TAPEOUT_CLASSPATH) &: $(TAPEOUT_SCALA_SOURCES) $(SCALA_BUILDTOOL_DEPS) $(TAPEOUT_VLOG_SOURCES) | $(GENERATOR_CLASSPATH) mkdir -p $(dir $@) $(call run_sbt_assembly,tapeout,$(TAPEOUT_CLASSPATH)) @@ -133,9 +133,9 @@ $(TAPEOUT_CLASSPATH) &: $(TAPEOUT_SCALA_SOURCES) $(SCALA_BUILDTOOL_DEPS) $(TAPEO # verilog generation pipeline ######################################################################################### # AG: must re-elaborate if cva6 sources have changed... otherwise just run firrtl compile -$(FIRRTL_FILE) $(ANNO_FILE) $(CHISEL_LOG_FILE) &: $(CHIPYARD_CLASSPATH) $(EXTRA_GENERATOR_REQS) +$(FIRRTL_FILE) $(ANNO_FILE) $(CHISEL_LOG_FILE) &: $(GENERATOR_CLASSPATH) $(EXTRA_GENERATOR_REQS) mkdir -p $(build_dir) - (set -o pipefail && $(call run_jar_scala_main,$(CHIPYARD_CLASSPATH),$(GENERATOR_PACKAGE).Generator,\ + (set -o pipefail && $(call run_jar_scala_main,$(GENERATOR_CLASSPATH),$(GENERATOR_PACKAGE).Generator,\ --target-dir $(build_dir) \ --name $(long_name) \ --top-module $(MODEL_PACKAGE).$(MODEL) \ diff --git a/variables.mk b/variables.mk index 9c7d159a..8fadc084 100644 --- a/variables.mk +++ b/variables.mk @@ -160,8 +160,8 @@ endif # classpaths CLASSPATH_CACHE ?= $(base_dir)/.classpath_cache -# The chipyard classpath must contain the Generator main -CHIPYARD_CLASSPATH ?= $(CLASSPATH_CACHE)/$(SBT_PROJECT).jar +# The generator classpath must contain the Generator main +GENERATOR_CLASSPATH ?= $(CLASSPATH_CACHE)/$(SBT_PROJECT).jar # The tapeout classpath must contain MacroCompiler TAPEOUT_CLASSPATH ?= $(CLASSPATH_CACHE)/tapeout.jar From 3cf3d815dc6a88113637be022e3aa0fda3a14763 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Thu, 16 May 2024 09:53:48 -0700 Subject: [PATCH 4/4] Rename fpga_platforms to chipyard_fpga --- build.sbt | 2 +- docs/Prototyping/General.rst | 2 +- fpga/Makefile | 10 +++++----- 3 files changed, 7 insertions(+), 7 deletions(-) diff --git a/build.sbt b/build.sbt index dd245a6f..fb38ee68 100644 --- a/build.sbt +++ b/build.sbt @@ -324,6 +324,6 @@ lazy val fpga_shells = (project in file("./fpga/fpga-shells")) .settings(libraryDependencies ++= rocketLibDeps.value) .settings(commonSettings) -lazy val fpga_platforms = (project in file("./fpga")) +lazy val chipyard_fpga = (project in file("./fpga")) .dependsOn(chipyard, fpga_shells) .settings(commonSettings) diff --git a/docs/Prototyping/General.rst b/docs/Prototyping/General.rst index 051cbcf8..17ef4173 100644 --- a/docs/Prototyping/General.rst +++ b/docs/Prototyping/General.rst @@ -30,7 +30,7 @@ For example: # converts to - make SBT_PROJECT=fpga_platforms MODEL=VCU118FPGATestHarness VLOG_MODEL=VCU118FPGATestHarness MODEL_PACKAGE=chipyard.fpga.vcu118 CONFIG=RocketVCU118Config CONFIG_PACKAGE=chipyard.fpga.vcu118 GENERATOR_PACKAGE=chipyard TB=none TOP=ChipTop BOARD=vcu118 FPGA_BRAND=... bitstream + make SBT_PROJECT=chipyard_fpga MODEL=VCU118FPGATestHarness VLOG_MODEL=VCU118FPGATestHarness MODEL_PACKAGE=chipyard.fpga.vcu118 CONFIG=RocketVCU118Config CONFIG_PACKAGE=chipyard.fpga.vcu118 GENERATOR_PACKAGE=chipyard TB=none TOP=ChipTop BOARD=vcu118 FPGA_BRAND=... bitstream Some ``SUB_PROJECT`` defaults are already defined for use, including ``vcu118`` and ``arty``. These default ``SUB_PROJECT``'s setup the necessary test harnesses, packages, and more for the Chipyard make system. diff --git a/fpga/Makefile b/fpga/Makefile index ebf55a97..22f7ce18 100644 --- a/fpga/Makefile +++ b/fpga/Makefile @@ -17,7 +17,7 @@ sim_name := none SUB_PROJECT ?= vcu118 ifeq ($(SUB_PROJECT),vc707) - SBT_PROJECT ?= fpga_platforms + SBT_PROJECT ?= chipyard_fpga MODEL ?= VC707FPGATestHarness VLOG_MODEL ?= VC707FPGATestHarness MODEL_PACKAGE ?= chipyard.fpga.vc707 @@ -31,7 +31,7 @@ ifeq ($(SUB_PROJECT),vc707) endif ifeq ($(SUB_PROJECT),vcu118) - SBT_PROJECT ?= fpga_platforms + SBT_PROJECT ?= chipyard_fpga MODEL ?= VCU118FPGATestHarness VLOG_MODEL ?= VCU118FPGATestHarness MODEL_PACKAGE ?= chipyard.fpga.vcu118 @@ -45,7 +45,7 @@ ifeq ($(SUB_PROJECT),vcu118) endif ifeq ($(SUB_PROJECT),nexysvideo) - SBT_PROJECT ?= fpga_platforms + SBT_PROJECT ?= chipyard_fpga MODEL ?= NexysVideoHarness VLOG_MODEL ?= NexysVideoHarness MODEL_PACKAGE ?= chipyard.fpga.nexysvideo @@ -60,7 +60,7 @@ endif ifeq ($(SUB_PROJECT),arty35t) # TODO: Fix with Arty - SBT_PROJECT ?= fpga_platforms + SBT_PROJECT ?= chipyard_fpga MODEL ?= Arty35THarness VLOG_MODEL ?= Arty35THarness MODEL_PACKAGE ?= chipyard.fpga.arty @@ -74,7 +74,7 @@ ifeq ($(SUB_PROJECT),arty35t) endif ifeq ($(SUB_PROJECT),arty100t) # TODO: Fix with Arty - SBT_PROJECT ?= fpga_platforms + SBT_PROJECT ?= chipyard_fpga MODEL ?= Arty100THarness VLOG_MODEL ?= Arty100THarness MODEL_PACKAGE ?= chipyard.fpga.arty100t