merge master
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@@ -1,15 +1,14 @@
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// See LICENSE for license details.
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// See LICENSE for license details.
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val defaultVersions = Map(
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val defaultVersions = Map(
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"chisel3" -> "3.5.1",
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"chisel3" -> "3.5.5",
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"chisel-iotesters" -> "2.5.1"
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"chisel-iotesters" -> "2.5.5"
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)
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)
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organization := "edu.berkeley.cs"
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organization := "edu.berkeley.cs"
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version := "0.4-SNAPSHOT"
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version := "0.4-SNAPSHOT"
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name := "tapeout"
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name := "tapeout"
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scalaVersion := "2.12.13"
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scalaVersion := "2.13.10"
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crossScalaVersions := Seq("2.12.13", "2.13.6")
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scalacOptions := Seq("-deprecation", "-feature", "-language:reflectiveCalls")
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scalacOptions := Seq("-deprecation", "-feature", "-language:reflectiveCalls")
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Test / scalacOptions ++= Seq("-language:reflectiveCalls")
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Test / scalacOptions ++= Seq("-language:reflectiveCalls")
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fork := true
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fork := true
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@@ -1 +1 @@
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sbt.version=1.3.13
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sbt.version=1.8.2
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@@ -14,7 +14,7 @@ class ExtraLowTransforms extends Transform with DependencyAPIMigration {
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// this PropagatePresetAnnotations is needed to run the RemoveValidIf pass (that is removed from CIRCT).
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// this PropagatePresetAnnotations is needed to run the RemoveValidIf pass (that is removed from CIRCT).
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// additionally, since that pass isn't explicitly a prereq of the LowFormEmitter it
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// additionally, since that pass isn't explicitly a prereq of the LowFormEmitter it
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// needs to wrapped in this xform
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// needs to wrapped in this xform
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override def prerequisites: Seq[TransformDependency] = Forms.LowForm :+
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override def prerequisites: Seq[TransformDependency] = Forms.LowForm :+
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Dependency[firrtl.transforms.PropagatePresetAnnotations]
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Dependency[firrtl.transforms.PropagatePresetAnnotations]
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override def optionalPrerequisites: Seq[TransformDependency] = Forms.LowFormOptimized
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override def optionalPrerequisites: Seq[TransformDependency] = Forms.LowFormOptimized
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override def optionalPrerequisiteOf: Seq[TransformDependency] = Forms.LowEmitters
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override def optionalPrerequisiteOf: Seq[TransformDependency] = Forms.LowEmitters
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@@ -1,50 +0,0 @@
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// See LICENSE for license details.
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package barstools.tapeout.transforms
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import chisel3._
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import chisel3.stage.{ChiselGeneratorAnnotation, ChiselStage}
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import firrtl.{EmittedFirrtlCircuitAnnotation, EmittedFirrtlModuleAnnotation}
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import org.scalatest.freespec.AnyFreeSpec
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import org.scalatest.matchers.should.Matchers
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class ExampleModuleNeedsResetInverted extends Module with ResetInverter {
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val io = IO(new Bundle {
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val out = Output(UInt(32.W))
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})
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val r = RegInit(0.U)
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io.out := r
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invert(this)
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}
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class ResetNSpec extends AnyFreeSpec with Matchers {
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"Inverting reset needs to be done throughout module in Chirrtl" in {
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val chirrtl = (new ChiselStage)
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.emitChirrtl(new ExampleModuleNeedsResetInverted, Array("--target-dir", "test_run_dir/reset_n_spec"))
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chirrtl should include("input reset :")
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(chirrtl should not).include("input reset_n :")
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(chirrtl should not).include("node reset = not(reset_n)")
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}
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"Inverting reset needs to be done throughout module when generating firrtl" in {
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// generate low-firrtl
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val firrtl = (new ChiselStage)
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.execute(
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Array("-X", "low", "--target-dir", "test_run_dir/reset_inverting_spec"),
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Seq(ChiselGeneratorAnnotation(() => new ExampleModuleNeedsResetInverted))
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)
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.collect {
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case EmittedFirrtlCircuitAnnotation(a) => a
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case EmittedFirrtlModuleAnnotation(a) => a
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}
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.map(_.value)
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.mkString("")
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firrtl should include("input reset_n :")
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firrtl should include("node reset = not(reset_n)")
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(firrtl should not).include("input reset :")
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}
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}
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