Subsystem done

This commit is contained in:
Zitao Fang
2020-05-25 13:58:04 -07:00
parent c0bafa306c
commit 2edfcb9022
2 changed files with 32 additions and 34 deletions

View File

@@ -17,9 +17,8 @@ import ariane.{ArianeTile, ArianeTilesKey, ArianeCrossingKey, ArianeTileParams}
// Third-party core entries
sealed trait CoreEntryBase {
def updateWithFilter(view: View, p: Any => View): (Map[String, Any] => PartialFunction[Any, Seq[AnyRef]])
def instantiateTile(param: TileParams, crossing: RocketCrossingParams,
logicalTreeNode: LogicalTreeNode, p: Parameters): Option[BaseTile]
def instantiateTile(crossingLookup: (Seq[RocketCrossingParams], Int) => ClockCrossingType)
(implicit logicalTreeNode: LogicalTreeNode, p: Parameters): (CoreParams, ClockCrossingType, BaseTile)
}
class CoreEntry[TileParamsT <: CoreParams, TileT <: BaseTile](
@@ -48,20 +47,18 @@ class CoreEntry[TileParamsT <: CoreParams, TileT <: BaseTile](
(tile => properties => copyTileParam(tile, properties))
}
def instantiateTile(param: TileParams, crossing: RocketCrossingParams,
logicalTreeNode: LogicalTreeNode, p: Parameters): Option[BaseTile] = param match {
case a: TileParams => Some(tileCtr.newInstance(a, crossing, PriorityMuxHartIdFromSeq(p(tilesKey)), logicalTreeNode, p))
case _ => None
def instantiateTile(crossingLookup: (Seq[RocketCrossingParams], Int) => ClockCrossingType)
(implicit logicalTreeNode: LogicalTreeNode, p: Parameters) = {
val tileParams = p(tk)
val crossings = crossingLookup(p(ck), tileParams.size)
(tileParams zip crossings) map ((param, crossing) => (
param,
crossing,
LazyModule(tileCtr(param, crossing, PriorityMuxHartIdFromSeq(tileParams), logicalTreeNode))
))
}
}
object CoreManager {
val cores: List[CoreEntryBase] = List(
// ADD YOUR CORE DEFINITION HERE
new CoreEntry[ArianeTileParams, ArianeTile](ArianeTilesKey, ArianeCrossingKey)
)
}
// Core Generic Config - change properties in the given map
class GenericConfig(properties: Map[String, Any], filterFunc: Any => Bool) {
val configFunc: (View, View, View) => PartialFunction[Any, Any] = ((site, here, up) => key => {
@@ -74,3 +71,10 @@ object GenericConfig {
def apply(properties: Map[String, Any], filterFunc: Any => Bool = (_ => true)) =
new GenericConfig(properties, filterFunc).configFunc
}
object CoreManager {
val cores: List[CoreEntryBase] = List(
// ADD YOUR CORE DEFINITION HERE
new CoreEntry[ArianeTileParams, ArianeTile](ArianeTilesKey, ArianeCrossingKey)
)
}

View File

@@ -35,18 +35,25 @@ trait HasChipyardTiles extends HasTiles
protected val rocketTileParams = p(RocketTilesKey)
protected val boomTileParams = p(BoomTilesKey)
protected val coreTileParams = CoreRegistrar.cores map (coreType => p(coreType.tilesKey))
// crossing can either be per tile or global (aka only 1 crossing specified)
private val rocketCrossings = perTileOrGlobalSetting(p(RocketCrossingKey), rocketTileParams.size)
private val boomCrossings = perTileOrGlobalSetting(p(BoomCrossingKey), boomTileParams.size)
private val coreCrossings = (CoreRegistrar.cores zip coreTileParams) map (_ match {
case (coreType, tileParams) => perTileOrGlobalSetting(p(coreType.crossingKey), tileParams.size)
})
// TODO: XXX The "tiles" below scan for hartId but it is not in CoreParams. Should that be added in later
private val rocketTilesInfo = (rocketTileParams zip rocketCrossings) map ((param, crossing) => (
param,
crossing,
LazyModule(new RocketTile(param, crossing, PriorityMuxHartIdFromSeq(rocketTileParams), logicalTreeNode))
))
private val boomTilesInfo = (boomTileParams zip boomCrossings) map ((param, crossing) => (
param,
crossing,
LazyModule(new RocketTile(param, crossing, PriorityMuxHartIdFromSeq(boomCrossings), logicalTreeNode))
))
// TODO: XXX The "tiles" below scan for hartId but it is not in CoreParams. Should that be added in later
// revision, or I have to use reflection to get that parameter?
val allTilesInfo = (rocketTileParams ++ boomTileParams ++ coreTileParams.flatten) zip (rocketCrossings ++ boomCrossings ++ coreCrossings.flatten)
val allTilesInfo = rocketTilesInfo ++ boomTilesInfo ++ (CoreManager.cores map _.instantiateTile(perTileOrGlobalSetting _))
// Make a tile and wire its nodes into the system,
// according to the specified type of clock crossing.
@@ -56,19 +63,7 @@ trait HasChipyardTiles extends HasTiles
// There is something weird with registering tile-local interrupt controllers to the CLINT.
// TODO: investigate why
val tiles = allTilesInfo.sortWith(_._1.hartId < _._1.hartId).map {
case (param, crossing) => {
val tile = param match {
case r: RocketTileParams => {
LazyModule(new RocketTile(r, crossing, PriorityMuxHartIdFromSeq(rocketTileParams), logicalTreeNode))
}
case b: BoomTileParams => {
LazyModule(new BoomTile(b, crossing, PriorityMuxHartIdFromSeq(boomTileParams), logicalTreeNode))
}
case _ => LazyModule(
(CoreRegistrar.cores collect (core => core.instantiateTile(param, crossing, paramList, logicalTreeNode, p)).unlift()) (0)
)
}
case (param, crossing, tile) => {
connectMasterPortsToSBus(tile, crossing)
connectSlavePortsToCBus(tile, crossing)
connectInterrupts(tile, debugOpt, clintOpt, plicOpt)
@@ -77,7 +72,6 @@ trait HasChipyardTiles extends HasTiles
}
}
def coreMonitorBundles = tiles.map {
case r: RocketTile => r.module.core.rocketImpl.coreMonitorBundle
case b: BoomTile => b.module.core.coreMonitorBundle