change dir structure

This commit is contained in:
alonamid
2019-03-07 14:18:24 -08:00
committed by abejgonzalez
parent 17c38a502a
commit 2def0dfea7
11 changed files with 17 additions and 17 deletions

2
sims/vsim/.gitignore vendored Normal file
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@@ -0,0 +1,2 @@
!Makefile
!.gitignore

84
sims/vsim/Makefile Normal file
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base_dir=$(abspath ../..)
sim_dir=$(abspath .)
PROJECT ?= example
MODEL ?= TestHarness
CONFIG ?= DefaultExampleConfig
CFG_PROJECT ?= $(PROJECT)
TB ?= TestDriver
TOP ?= ExampleTop
sim_name = vcs
simv = $(sim_dir)/simv-$(PROJECT)-$(CONFIG)
simv_debug = $(sim_dir)/simv-$(PROJECT)-$(CONFIG)-debug
default: $(simv)
debug: $(simv_debug)
include $(base_dir)/Makefrag
ifneq ($(filter run% %.run %.out %.vpd %.vcd,$(MAKECMDGOALS)),)
-include $(build_dir)/$(long_name).d
endif
sim_blackboxes = \
$(build_dir)/firrtl_black_box_resource_files.f
rocketchip_vsrc_dir = $(ROCKETCHIP_DIR)/src/main/resources/vsrc
sim_vsrcs = \
$(VERILOG_FILE) \
$(HARNESS_FILE) \
$(SMEMS_FILE)
VCS = vcs -full64
VCS_OPTS = -notice -line +lint=all,noVCDE,noONGS,noUI -error=PCWM-L -timescale=1ns/10ps -quiet \
+rad +v2k +vcs+lic+wait \
+vc+list -CC "-I$(VCS_HOME)/include" \
-CC "-I$(RISCV)/include" \
-CC "-std=c++11" \
-CC "-Wl,-rpath,$(RISCV)/lib" \
-f $(sim_blackboxes) -f $(sim_dotf) \
$(RISCV)/lib/libfesvr.so \
-sverilog \
+incdir+$(generated_dir) \
+define+CLOCK_PERIOD=1.0 $(sim_vsrcs) \
+define+PRINTF_COND=$(TB).printf_cond \
+define+STOP_COND=!$(TB).reset \
+define+RANDOMIZE_MEM_INIT \
+define+RANDOMIZE_REG_INIT \
+define+RANDOMIZE_GARBAGE_ASSIGN \
+define+RANDOMIZE_INVALID_ASSIGN \
+libext+.v \
verilog: $(sim_vsrcs)
$(simv): $(sim_vsrcs) $(sim_dotf)
rm -rf csrc && $(VCS) $(VCS_OPTS) -o $@ \
-debug_pp
$(simv_debug) : $(sim_vsrcs) $(sim_dotf)
rm -rf csrc && $(VCS) $(VCS_OPTS) -o $@ \
+define+DEBUG -debug_pp
$(output_dir)/%.out: $(output_dir)/% $(simv)
$(simv) +verbose +max-cycles=1000000 $< 3>&1 1>&2 2>&3 | spike-dasm > $@
$(output_dir)/%.run: $(output_dir)/% $(simv)
$(simv) +max-cycles=1000000 $< && touch $@
$(output_dir)/%.vpd: $(output_dir)/% $(simv_debug)
$(simv_debug) +vcdplusfile=$@ +max-cycles=1000000 $<
run-regression-tests: $(addprefix $(output_dir)/,$(addsuffix .out,$(regression-tests)))
run-regression-tests-fast: $(addprefix $(output_dir)/,$(addsuffix .run,$(regression-tests)))
run-regression-tests-debug: $(addprefix $(output_dir)/,$(addsuffix .vpd,$(regression-tests)))
clean:
rm -rf generated-src csrc simv-* ucli.key vc_hdrs.h
.PHONY: clean