[ci skip] Note that CVA6 was called Ariane in the past

docs/Chipyard-Basics/Chipyard-Components.rst

@@ -21,7 +21,7 @@ Processor Cores
   See :ref:`Berkeley Out-of-Order Machine (BOOM)` for more information.
 
 **CVA6 Core**
-  An in-order RISC-V core written in System Verilog.
+  An in-order RISC-V core written in System Verilog. Previously called Ariane.
   See :ref:`CVA6 Core` for more information.
 
 Accelerators

docs/Generators/CVA6.rst

@@ -1,7 +1,7 @@
 CVA6 Core
 ====================================
 
-`CVA6 <https://github.com/openhwgroup/cva6>`__ is a 6-stage in-order scalar processor core, originally developed at ETH-Zurich by F. Zaruba and L. Benini.
+`CVA6 <https://github.com/openhwgroup/cva6>`__ (previously called Ariane) is a 6-stage in-order scalar processor core, originally developed at ETH-Zurich by F. Zaruba and L. Benini.
 The `CVA6 core` is wrapped in an `CVA6 tile` so it can be used as a component within the `Rocket Chip SoC generator`.
 The core by itself exposes an AXI interface, interrupt ports, and other misc. ports that are connected from within the tile to TileLink buses and other parameterization signals.