From 700f68730b0106a82103c4b88b913a369606df30 Mon Sep 17 00:00:00 2001 From: Zitao Fang Date: Fri, 14 Aug 2020 17:52:36 -0700 Subject: [PATCH 01/11] Fix verilator makefile --- sims/verilator/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/verilator/Makefile b/sims/verilator/Makefile index 3d676efd..f093fa2d 100644 --- a/sims/verilator/Makefile +++ b/sims/verilator/Makefile @@ -28,7 +28,7 @@ sim_prefix = simulator sim = $(sim_dir)/$(sim_prefix)-$(MODEL_PACKAGE)-$(CONFIG) sim_debug = $(sim_dir)/$(sim_prefix)-$(MODEL_PACKAGE)-$(CONFIG)-debug -WAVEFORM_FLAG=-v$(sim_out_name).vcd +WAVEFORM_FLAG=-v $(sim_out_name).vcd # If verilator seed unspecified, verilator uses srand as random seed ifdef RANDOM_SEED From 5243ee2a35fd1ee2c3caba15df4e7eb0cc34d7a9 Mon Sep 17 00:00:00 2001 From: Zitao Fang Date: Fri, 25 Sep 2020 20:36:07 -0700 Subject: [PATCH 02/11] Add HTIF args back to emulator.cc --- generators/utilities/src/main/resources/csrc/emulator.cc | 9 ++++++++- sims/verilator/Makefile | 2 +- 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/generators/utilities/src/main/resources/csrc/emulator.cc b/generators/utilities/src/main/resources/csrc/emulator.cc index 5e0ea38b..88a6b26d 100644 --- a/generators/utilities/src/main/resources/csrc/emulator.cc +++ b/generators/utilities/src/main/resources/csrc/emulator.cc @@ -163,6 +163,7 @@ int main(int argc, char** argv) #if VM_TRACE case 'v': { vcdfile_name = optarg; + // printf("%s\n", vcdfile_name); vcdfile = strcmp(optarg, "-") == 0 ? stdout : fopen(optarg, "w"); if (!vcdfile) { std::cerr << "Unable to open " << optarg << " for VCD write\n"; @@ -258,6 +259,11 @@ done_processing: return 1; } + int htif_argc = 1 + argc - optind; + htif_argv = (char **) malloc((htif_argc) * sizeof (char *)); + htif_argv[0] = argv[0]; + for (int i = 1; optind < argc;) htif_argv[i++] = argv[optind++]; + if (verbose) fprintf(stderr, "using random seed %u\n", random_seed); @@ -265,7 +271,7 @@ done_processing: srand48(random_seed); Verilated::randReset(2); - Verilated::commandArgs(argc, argv); + Verilated::commandArgs(htif_argc, htif_argv); TEST_HARNESS *tile = new TEST_HARNESS; #if VM_TRACE @@ -374,5 +380,6 @@ done_processing: if (tsi) delete tsi; if (jtag) delete jtag; if (tile) delete tile; + if (htif_argv) free(htif_argv); return ret; } diff --git a/sims/verilator/Makefile b/sims/verilator/Makefile index 8c51098f..211b5676 100644 --- a/sims/verilator/Makefile +++ b/sims/verilator/Makefile @@ -28,7 +28,7 @@ sim_prefix = simulator sim = $(sim_dir)/$(sim_prefix)-$(MODEL_PACKAGE)-$(CONFIG) sim_debug = $(sim_dir)/$(sim_prefix)-$(MODEL_PACKAGE)-$(CONFIG)-debug -WAVEFORM_FLAG=-v $(sim_out_name).vcd +WAVEFORM_FLAG=-v$(sim_out_name).vcd # If verilator seed unspecified, verilator uses srand as random seed ifdef RANDOM_SEED From 751c0c300ef9e50ecc0805c566865ea2d043dbe0 Mon Sep 17 00:00:00 2001 From: Zitao Fang Date: Fri, 25 Sep 2020 20:49:18 -0700 Subject: [PATCH 03/11] Remove comments --- generators/utilities/src/main/resources/csrc/emulator.cc | 1 - 1 file changed, 1 deletion(-) diff --git a/generators/utilities/src/main/resources/csrc/emulator.cc b/generators/utilities/src/main/resources/csrc/emulator.cc index 88a6b26d..d6bca76b 100644 --- a/generators/utilities/src/main/resources/csrc/emulator.cc +++ b/generators/utilities/src/main/resources/csrc/emulator.cc @@ -163,7 +163,6 @@ int main(int argc, char** argv) #if VM_TRACE case 'v': { vcdfile_name = optarg; - // printf("%s\n", vcdfile_name); vcdfile = strcmp(optarg, "-") == 0 ? stdout : fopen(optarg, "w"); if (!vcdfile) { std::cerr << "Unable to open " << optarg << " for VCD write\n"; From 2aac38b4c81b9623d0a9112ce2dd10949f60b417 Mon Sep 17 00:00:00 2001 From: Zitao Fang Date: Sun, 27 Sep 2020 23:15:10 -0700 Subject: [PATCH 04/11] Fix CI bug --- generators/utilities/src/main/resources/csrc/emulator.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/utilities/src/main/resources/csrc/emulator.cc b/generators/utilities/src/main/resources/csrc/emulator.cc index d6bca76b..a670147d 100644 --- a/generators/utilities/src/main/resources/csrc/emulator.cc +++ b/generators/utilities/src/main/resources/csrc/emulator.cc @@ -259,7 +259,7 @@ done_processing: } int htif_argc = 1 + argc - optind; - htif_argv = (char **) malloc((htif_argc) * sizeof (char *)); + char** htif_argv = (char **) malloc((htif_argc) * sizeof (char *)); htif_argv[0] = argv[0]; for (int i = 1; optind < argc;) htif_argv[i++] = argv[optind++]; From 355e4ba60640724c4325f248e19982ec4e8bf4f4 Mon Sep 17 00:00:00 2001 From: Zitao Fang Date: Mon, 5 Oct 2020 10:49:04 -0700 Subject: [PATCH 05/11] Change to filter all arguments that begin with a '-' --- generators/utilities/src/main/resources/csrc/emulator.cc | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/generators/utilities/src/main/resources/csrc/emulator.cc b/generators/utilities/src/main/resources/csrc/emulator.cc index a670147d..f3c6dbdb 100644 --- a/generators/utilities/src/main/resources/csrc/emulator.cc +++ b/generators/utilities/src/main/resources/csrc/emulator.cc @@ -258,10 +258,11 @@ done_processing: return 1; } - int htif_argc = 1 + argc - optind; - char** htif_argv = (char **) malloc((htif_argc) * sizeof (char *)); + int htif_argc = 1; + char** htif_argv = new char*[argc]; htif_argv[0] = argv[0]; - for (int i = 1; optind < argc;) htif_argv[i++] = argv[optind++]; + for (int i = 1; i < argc; i++) + if (argv[i][0] != '-') htif_argv[htif_argc++] = argv[i]; if (verbose) fprintf(stderr, "using random seed %u\n", random_seed); @@ -379,6 +380,6 @@ done_processing: if (tsi) delete tsi; if (jtag) delete jtag; if (tile) delete tile; - if (htif_argv) free(htif_argv); + if (htif_argv) delete[] htif_argv; return ret; } From 5282965b5b52da2ede3ee2ec0ac5093b93fccd6a Mon Sep 17 00:00:00 2001 From: Zitao Fang Date: Tue, 6 Oct 2020 15:50:11 -0700 Subject: [PATCH 06/11] Filter specified HTIF arguments and plusargs only --- .../src/main/resources/csrc/emulator.cc | 23 +++++++++++++------ 1 file changed, 16 insertions(+), 7 deletions(-) diff --git a/generators/utilities/src/main/resources/csrc/emulator.cc b/generators/utilities/src/main/resources/csrc/emulator.cc index f3c6dbdb..f42f5bce 100644 --- a/generators/utilities/src/main/resources/csrc/emulator.cc +++ b/generators/utilities/src/main/resources/csrc/emulator.cc @@ -123,6 +123,10 @@ int main(int argc, char** argv) #endif int verilog_plusargs_legal = 1; + int verilated_argc = 1; + char** verilated_argv = new char*[argc]; + verilated_argv[0] = argv[0]; + opterr = 1; while (1) { @@ -195,9 +199,15 @@ int main(int argc, char** argv) else if (arg.substr(0, 12) == "+cycle-count") c = 'c'; else if (arg == "+permissive") + { c = 'p'; + verilated_argv[verilated_argc++] = optarg; + } else if (arg == "+permissive-off") + { c = 'o'; + verilated_argv[verilated_argc++] = optarg; + } // If we don't find a legacy '+' EMULATOR argument, it still could be // a VERILOG_PLUSARG and not an error. else if (verilog_plusargs_legal) { @@ -213,6 +223,7 @@ int main(int argc, char** argv) verilog_plusargs_legal = 0; } else { c = 'P'; + verilated_argv[verilated_argc++] = optarg; } goto retry; } @@ -235,6 +246,7 @@ int main(int argc, char** argv) c = '?'; } else { c = 'p'; + verilated_argv[verilated_argc++] = optarg; } } goto retry; @@ -258,11 +270,8 @@ done_processing: return 1; } - int htif_argc = 1; - char** htif_argv = new char*[argc]; - htif_argv[0] = argv[0]; - for (int i = 1; i < argc; i++) - if (argv[i][0] != '-') htif_argv[htif_argc++] = argv[i]; + // Copy the binary file name into the verilator argument stack + while (optind < argc) verilated_argv[verilated_argc++] = argv[optind++]; if (verbose) fprintf(stderr, "using random seed %u\n", random_seed); @@ -271,7 +280,7 @@ done_processing: srand48(random_seed); Verilated::randReset(2); - Verilated::commandArgs(htif_argc, htif_argv); + Verilated::commandArgs(verilated_argc, verilated_argv); TEST_HARNESS *tile = new TEST_HARNESS; #if VM_TRACE @@ -380,6 +389,6 @@ done_processing: if (tsi) delete tsi; if (jtag) delete jtag; if (tile) delete tile; - if (htif_argv) delete[] htif_argv; + if (verilated_argv) delete[] verilated_argv; return ret; } From ac19117ec5fc890b9c9b9540c3cb3f0c1ab65721 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Fri, 23 Oct 2020 15:41:49 -0700 Subject: [PATCH 07/11] Add MultiRoCCGemmini config fragment --- .../chipyard/src/main/scala/ConfigFragments.scala | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/generators/chipyard/src/main/scala/ConfigFragments.scala b/generators/chipyard/src/main/scala/ConfigFragments.scala index e66dfb4a..68c41724 100644 --- a/generators/chipyard/src/main/scala/ConfigFragments.scala +++ b/generators/chipyard/src/main/scala/ConfigFragments.scala @@ -18,6 +18,7 @@ import testchipip._ import tracegen.{TraceGenSystem} import hwacha.{Hwacha} +import gemmini.{Gemmini, GemminiConfigs} import boom.common.{BoomTileAttachParams} import ariane.{ArianeTileAttachParams} @@ -105,6 +106,16 @@ class WithMultiRoCCHwacha(harts: Int*) extends Config( }) ) +class WithMultiRoCCGemmini(harts: Int*) extends Config((site, here, up) => { + case MultiRoCCKey => up(MultiRoCCKey, site) ++ harts.distinct.map { i => + (i -> Seq((p: Parameters) => { + implicit val q = p + val gemmini = LazyModule(new Gemmini(OpcodeSet.custom3, GemminiConfigs.defaultConfig)) + gemmini + })) + } +}) + class WithTraceIO extends Config((site, here, up) => { case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map { case tp: BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy( From 0c4dcffb0d40fe0146b25fc4d7ad2dff94a0bd2c Mon Sep 17 00:00:00 2001 From: Zitao Fang Date: Fri, 23 Oct 2020 16:39:56 -0700 Subject: [PATCH 08/11] Fixed lowercase p bug --- generators/utilities/src/main/resources/csrc/emulator.cc | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/generators/utilities/src/main/resources/csrc/emulator.cc b/generators/utilities/src/main/resources/csrc/emulator.cc index f42f5bce..d3813bbd 100644 --- a/generators/utilities/src/main/resources/csrc/emulator.cc +++ b/generators/utilities/src/main/resources/csrc/emulator.cc @@ -223,7 +223,6 @@ int main(int argc, char** argv) verilog_plusargs_legal = 0; } else { c = 'P'; - verilated_argv[verilated_argc++] = optarg; } goto retry; } @@ -245,13 +244,14 @@ int main(int argc, char** argv) << arg << "\"\n"; c = '?'; } else { - c = 'p'; - verilated_argv[verilated_argc++] = optarg; + c = 'P'; } } goto retry; } - case 'P': break; // Nothing to do here, Verilog PlusArg + case 'P': + verilated_argv[verilated_argc++] = optarg; + break; // Nothing to do here, Verilog PlusArg // Realize that we've hit HTIF (HOST) arguments or error out default: if (c >= HTIF_LONG_OPTIONS_OPTIND) { From abbeb2af9e18417dfc6a363a7463373fa6920db3 Mon Sep 17 00:00:00 2001 From: Zitao Fang Date: Fri, 23 Oct 2020 17:00:56 -0700 Subject: [PATCH 09/11] Fixed comments --- generators/utilities/src/main/resources/csrc/emulator.cc | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/generators/utilities/src/main/resources/csrc/emulator.cc b/generators/utilities/src/main/resources/csrc/emulator.cc index d3813bbd..40b5a2fa 100644 --- a/generators/utilities/src/main/resources/csrc/emulator.cc +++ b/generators/utilities/src/main/resources/csrc/emulator.cc @@ -249,9 +249,9 @@ int main(int argc, char** argv) } goto retry; } - case 'P': + case 'P': // Verilog PlusArg, add to the argument list for verilator environment verilated_argv[verilated_argc++] = optarg; - break; // Nothing to do here, Verilog PlusArg + break; // Realize that we've hit HTIF (HOST) arguments or error out default: if (c >= HTIF_LONG_OPTIONS_OPTIND) { @@ -270,7 +270,7 @@ done_processing: return 1; } - // Copy the binary file name into the verilator argument stack + // Copy remaining HTIF arguments (if any) and the binary file name into the verilator argument stack while (optind < argc) verilated_argv[verilated_argc++] = argv[optind++]; if (verbose) From 93e57ef23096528a6edd36c52e0ae69b6e629d06 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Mon, 26 Oct 2020 15:18:34 -0700 Subject: [PATCH 10/11] Make the ChipTop reset pin async always --- .../chipyard/src/main/scala/Clocks.scala | 52 +++---------------- .../chipyard/src/main/scala/IOBinders.scala | 18 +++---- .../chipyard/src/main/scala/TestHarness.scala | 3 +- 3 files changed, 15 insertions(+), 58 deletions(-) diff --git a/generators/chipyard/src/main/scala/Clocks.scala b/generators/chipyard/src/main/scala/Clocks.scala index 70fe38e7..3c9e70cd 100644 --- a/generators/chipyard/src/main/scala/Clocks.scala +++ b/generators/chipyard/src/main/scala/Clocks.scala @@ -15,40 +15,6 @@ import testchipip.{TLTileResetCtrl} import chipyard.clocking._ -/** - * Chipyard provides three baseline, top-level reset schemes, set using the - * [[GlobalResetSchemeKey]] in a Parameters instance. These are: - * - * 1) Synchronous: The input coming to the chip is synchronous to the provided - * clocks and will be used without modification as a synchronous reset. - * This is safe only for use in FireSim and SW simulation. - * - * 2) Asynchronous: The input reset is asynchronous to the input clock, but it - * is caught and synchronized to that clock before it is dissemenated. - * Thus, downsteam modules will be emitted with synchronously reset state - * elements. - * - * 3) Asynchronous Full: The input reset is asynchronous to the input clock, - * and is used globally as an async reset. Downstream modules will be emitted - * with asynchronously reset state elements. - * - */ -sealed trait GlobalResetScheme { - def pinIsAsync: Boolean -} -sealed trait HasAsyncInput { self: GlobalResetScheme => - def pinIsAsync = true -} - -sealed trait HasSyncInput { self: GlobalResetScheme => - def pinIsAsync = false -} - -case object GlobalResetSynchronous extends GlobalResetScheme with HasSyncInput -case object GlobalResetAsynchronous extends GlobalResetScheme with HasAsyncInput -case object GlobalResetAsynchronousFull extends GlobalResetScheme with HasAsyncInput -case object GlobalResetSchemeKey extends Field[GlobalResetScheme](GlobalResetSynchronous) - /** * A simple reset implementation that punches out reset ports * for standard Module classes. Three basic reset schemes @@ -58,18 +24,12 @@ object GenerateReset { def apply(chiptop: ChipTop, clock: Clock): Reset = { implicit val p = chiptop.p // this needs directionality so generateIOFromSignal works - val reset_wire = Wire(Input(Reset())) - val (reset_io, resetIOCell) = p(GlobalResetSchemeKey) match { - case GlobalResetSynchronous => - IOCell.generateIOFromSignal(reset_wire, "reset") - case GlobalResetAsynchronousFull => - IOCell.generateIOFromSignal(reset_wire, "reset", abstractResetAsAsync = true) - case GlobalResetAsynchronous => { - val async_reset_wire = Wire(Input(AsyncReset())) - reset_wire := ResetCatchAndSync(clock, async_reset_wire.asBool()) - IOCell.generateIOFromSignal(async_reset_wire, "reset", abstractResetAsAsync = true) - } - } + val async_reset_wire = Wire(Input(AsyncReset())) + val (reset_io, resetIOCell) = IOCell.generateIOFromSignal(async_reset_wire, "reset", + abstractResetAsAsync = true) + + val reset_wire = ResetCatchAndSync(clock, async_reset_wire.asBool()) + chiptop.iocells ++= resetIOCell chiptop.harnessFunctions += ((th: HasHarnessSignalReferences) => { reset_io := th.dutReset diff --git a/generators/chipyard/src/main/scala/IOBinders.scala b/generators/chipyard/src/main/scala/IOBinders.scala index 87480bfc..246d9c3d 100644 --- a/generators/chipyard/src/main/scala/IOBinders.scala +++ b/generators/chipyard/src/main/scala/IOBinders.scala @@ -24,8 +24,6 @@ import barstools.iocell.chisel._ import testchipip._ import icenet.{CanHavePeripheryIceNIC, SimNetwork, NicLoopback, NICKey, NICIOvonly} -import chipyard.GlobalResetSchemeKey - import scala.reflect.{ClassTag} // System for instantiating binders based @@ -157,7 +155,7 @@ class WithGPIOCells extends OverrideIOBinder({ class WithUARTIOCells extends OverrideIOBinder({ (system: HasPeripheryUARTModuleImp) => { val (ports: Seq[UARTPortIO], cells2d) = system.uart.zipWithIndex.map({ case (u, i) => - val (port, ios) = IOCell.generateIOFromSignal(u, s"uart_${i}", system.p(IOCellKey)) + val (port, ios) = IOCell.generateIOFromSignal(u, s"uart_${i}", system.p(IOCellKey), abstractResetAsAsync = true) (port, ios) }).unzip (ports, cells2d.flatten) @@ -173,8 +171,8 @@ class WithSPIIOCells extends OverrideIOBinder({ val iocellBase = s"iocell_${name}" // SCK and CS are unidirectional outputs - val sckIOs = IOCell.generateFromSignal(s.sck, port.sck, Some(s"${iocellBase}_sck"), system.p(IOCellKey)) - val csIOs = IOCell.generateFromSignal(s.cs, port.cs, Some(s"${iocellBase}_cs"), system.p(IOCellKey)) + val sckIOs = IOCell.generateFromSignal(s.sck, port.sck, Some(s"${iocellBase}_sck"), system.p(IOCellKey), IOCell.toAsyncReset) + val csIOs = IOCell.generateFromSignal(s.cs, port.cs, Some(s"${iocellBase}_cs"), system.p(IOCellKey), IOCell.toAsyncReset) // DQ are bidirectional, so then need special treatment val dqIOs = s.dq.zip(port.dq).zipWithIndex.map { case ((pin, ana), j) => @@ -196,7 +194,7 @@ class WithSPIIOCells extends OverrideIOBinder({ class WithExtInterruptIOCells extends OverrideIOBinder({ (system: HasExtInterruptsModuleImp) => { if (system.outer.nExtInterrupts > 0) { - val (port: UInt, cells) = IOCell.generateIOFromSignal(system.interrupts, "ext_interrupts", system.p(IOCellKey)) + val (port: UInt, cells) = IOCell.generateIOFromSignal(system.interrupts, "ext_interrupts", system.p(IOCellKey), abstractResetAsAsync = true) (Seq(port), cells) } else { (Nil, Nil) @@ -240,15 +238,15 @@ class WithDebugIOCells extends OverrideIOBinder({ // Add IOCells for the DMI/JTAG/APB ports val dmiTuple = debug.clockeddmi.map { d => - IOCell.generateIOFromSignal(d, "dmi", p(IOCellKey), abstractResetAsAsync = p(GlobalResetSchemeKey).pinIsAsync) + IOCell.generateIOFromSignal(d, "dmi", p(IOCellKey), abstractResetAsAsync = true) } val jtagTuple = debug.systemjtag.map { j => - IOCell.generateIOFromSignal(j.jtag, "jtag", p(IOCellKey), abstractResetAsAsync = p(GlobalResetSchemeKey).pinIsAsync) + IOCell.generateIOFromSignal(j.jtag, "jtag", p(IOCellKey), abstractResetAsAsync = true) } val apbTuple = debug.apb.map { a => - IOCell.generateIOFromSignal(a, "apb", p(IOCellKey), abstractResetAsAsync = p(GlobalResetSchemeKey).pinIsAsync) + IOCell.generateIOFromSignal(a, "apb", p(IOCellKey), abstractResetAsAsync = true) } val allTuples = (dmiTuple ++ jtagTuple ++ apbTuple).toSeq @@ -260,7 +258,7 @@ class WithDebugIOCells extends OverrideIOBinder({ class WithSerialTLIOCells extends OverrideIOBinder({ (system: CanHavePeripheryTLSerial) => system.serial_tl.map({ s => val sys = system.asInstanceOf[BaseSubsystem] - val (port, cells) = IOCell.generateIOFromSignal(s.getWrappedValue, "serial_tl", sys.p(IOCellKey)) + val (port, cells) = IOCell.generateIOFromSignal(s.getWrappedValue, "serial_tl", sys.p(IOCellKey), abstractResetAsAsync = true) (Seq(port), cells) }).getOrElse((Nil, Nil)) }) diff --git a/generators/chipyard/src/main/scala/TestHarness.scala b/generators/chipyard/src/main/scala/TestHarness.scala index 2faff565..0b49d03c 100644 --- a/generators/chipyard/src/main/scala/TestHarness.scala +++ b/generators/chipyard/src/main/scala/TestHarness.scala @@ -39,8 +39,7 @@ class TestHarness(implicit val p: Parameters) extends Module with HasHarnessSign val harnessReset = WireInit(reset) val success = io.success - // dutReset assignment can be overridden via a harnessFunction, but by default it is just reset - val dutReset = WireDefault(if (p(GlobalResetSchemeKey).pinIsAsync) reset.asAsyncReset else reset) + val dutReset = reset.asAsyncReset lazyDut match { case d: HasTestHarnessFunctions => d.harnessFunctions.foreach(_(this)) From f4d70128c007807ba7617f5c4fd47ebaf59c49c4 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Wed, 28 Oct 2020 15:34:14 -0700 Subject: [PATCH 11/11] Remove redundant ChipTop reset synchronizer --- generators/chipyard/src/main/scala/Clocks.scala | 4 +--- .../chipyard/src/main/scala/clocking/ResetSynchronizer.scala | 2 +- 2 files changed, 2 insertions(+), 4 deletions(-) diff --git a/generators/chipyard/src/main/scala/Clocks.scala b/generators/chipyard/src/main/scala/Clocks.scala index 3c9e70cd..e4d48b59 100644 --- a/generators/chipyard/src/main/scala/Clocks.scala +++ b/generators/chipyard/src/main/scala/Clocks.scala @@ -28,14 +28,12 @@ object GenerateReset { val (reset_io, resetIOCell) = IOCell.generateIOFromSignal(async_reset_wire, "reset", abstractResetAsAsync = true) - val reset_wire = ResetCatchAndSync(clock, async_reset_wire.asBool()) - chiptop.iocells ++= resetIOCell chiptop.harnessFunctions += ((th: HasHarnessSignalReferences) => { reset_io := th.dutReset Nil }) - reset_wire + async_reset_wire } } diff --git a/generators/chipyard/src/main/scala/clocking/ResetSynchronizer.scala b/generators/chipyard/src/main/scala/clocking/ResetSynchronizer.scala index 13a593c5..2ba8e855 100644 --- a/generators/chipyard/src/main/scala/clocking/ResetSynchronizer.scala +++ b/generators/chipyard/src/main/scala/clocking/ResetSynchronizer.scala @@ -12,7 +12,7 @@ import freechips.rocketchip.util.{ResetCatchAndSync} * Instantiates a reset synchronizer on all clock-reset pairs in a clock group */ class ClockGroupResetSynchronizer(implicit p: Parameters) extends LazyModule { - val node = ClockGroupIdentityNode() + val node = ClockGroupAdapterNode() lazy val module = new LazyRawModuleImp(this) { (node.out zip node.in).map { case ((oG, _), (iG, _)) => (oG.member.data zip iG.member.data).foreach { case (o, i) =>