Merge remote-tracking branch 'upstream/main' into graphics

rocket-chip not yet merged

generators/chipyard/src/main/scala/DigitalTop.scala

@@ -41,6 +41,7 @@ class DigitalTop(implicit p: Parameters) extends ChipyardSystem
   with chipyard.clocking.CanHaveClockTap // Enables optionally adding a clock tap output port
   with fftgenerator.CanHavePeripheryFFT // Enables optionally having an MMIO-based FFT block
   with constellation.soc.CanHaveGlobalNoC // Support instantiating a global NoC interconnect
+  with rerocc.CanHaveReRoCCTiles // Support tiles that instantiate rerocc-attached accelerators
 {
   override lazy val module = new DigitalTopModule(this)
 }

generators/chipyard/src/main/scala/SpikeTile.scala

@@ -14,7 +14,7 @@ import freechips.rocketchip.tilelink._
 import freechips.rocketchip.interrupts._
 import freechips.rocketchip.util._
 import freechips.rocketchip.tile._
-import freechips.rocketchip.prci.ClockSinkParameters
+import freechips.rocketchip.prci._
 
 case class SpikeCoreParams() extends CoreParams {
   val useVM = true

generators/chipyard/src/main/scala/clocking/ClockBinders.scala

@@ -27,9 +27,9 @@ class WithPLLSelectorDividerClockGenerator(enable: Boolean = true) extends Overr
     val clockSelector = system.prci_ctrl_domain { LazyModule(new TLClockSelector(baseAddress + 0x30000, tlbus.beatBytes, enable=enable)) }
     val pllCtrl       = system.prci_ctrl_domain { LazyModule(new FakePLLCtrl    (baseAddress + 0x40000, tlbus.beatBytes)) }
 
-    clockDivider.tlNode  := system.prci_ctrl_domain { TLFragmenter(tlbus.beatBytes, tlbus.blockBytes) := system.prci_ctrl_bus.get }
-    clockSelector.tlNode := system.prci_ctrl_domain { TLFragmenter(tlbus.beatBytes, tlbus.blockBytes) := system.prci_ctrl_bus.get }
-    pllCtrl.tlNode       := system.prci_ctrl_domain { TLFragmenter(tlbus.beatBytes, tlbus.blockBytes) := system.prci_ctrl_bus.get }
+    clockDivider.tlNode  := system.prci_ctrl_domain { TLFragmenter(tlbus, Some("ClockDivider")) := system.prci_ctrl_bus.get }
+    clockSelector.tlNode := system.prci_ctrl_domain { TLFragmenter(tlbus, Some("ClockSelector")) := system.prci_ctrl_bus.get }
+    pllCtrl.tlNode       := system.prci_ctrl_domain { TLFragmenter(tlbus, Some("PLLCtrl")) := system.prci_ctrl_bus.get }
 
     system.chiptopClockGroupsNode := clockDivider.clockNode := clockSelector.clockNode
 
@@ -72,7 +72,7 @@ class WithPLLSelectorDividerClockGenerator(enable: Boolean = true) extends Overr
     }
   }
 })
- 
+
 // This passes all clocks through to the TestHarness
 class WithPassthroughClockGenerator extends OverrideLazyIOBinder({
   (system: HasChipyardPRCI) => {
@@ -102,6 +102,32 @@ class WithPassthroughClockGenerator extends OverrideLazyIOBinder({
   }
 })
 
+// Broadcasts a single clock IO to all clock domains. Ignores all requested frequencies
+class WithSingleClockBroadcastClockGenerator(freqMHz: Int = 100) extends OverrideLazyIOBinder({
+  (system: HasChipyardPRCI) => {
+    implicit val p = GetSystemParameters(system)
+
+    val clockGroupsAggregator = LazyModule(new ClockGroupAggregator("single_clock"))
+    val clockGroupsSourceNode = ClockGroupSourceNode(Seq(ClockGroupSourceParameters()))
+    system.chiptopClockGroupsNode :*= clockGroupsAggregator.node := clockGroupsSourceNode
+
+    InModuleBody {
+      val clock_wire = Wire(Input(Clock()))
+      val reset_wire = Wire(Input(AsyncReset()))
+      val (clock_io, clockIOCell) = IOCell.generateIOFromSignal(clock_wire, "clock", p(IOCellKey))
+      val (reset_io, resetIOCell) = IOCell.generateIOFromSignal(reset_wire, "reset", p(IOCellKey))
+
+      clockGroupsSourceNode.out.foreach { case (bundle, edge) =>
+        bundle.member.data.foreach { b =>
+          b.clock := clock_io
+          b.reset := reset_io
+        }
+      }
+      (Seq(ClockPort(() => clock_io, freqMHz), ResetPort(() => reset_io)), clockIOCell ++ resetIOCell)
+    }
+  }
+})
+
 class WithClockTapIOCells extends OverrideIOBinder({
   (system: CanHaveClockTap) => {
     system.clockTapIO.map { tap =>

generators/chipyard/src/main/scala/clocking/ClockGroupCombiner.scala

@@ -48,9 +48,10 @@ class ClockGroupCombiner(implicit p: Parameters, v: ValName) extends LazyModule
       val name = combiners(i)._1
       i = i + 1
       require(g.size >= 1)
+      val names = g.map(_.name.getOrElse("unamed"))
       val takes = g.map(_.take).flatten
       require(takes.distinct.size <= 1,
-        s"Clock group $name has non-homogeneous requested ClockParameters $takes")
+        s"Clock group $name has non-homogeneous requested ClockParameters ${names.zip(takes)}")
       require(takes.size > 0,
         s"Clock group $name has no inheritable frequencies")
       (grouped ++ Seq(ClockSinkParameters(take = takes.headOption, name = Some(name))), r)

generators/chipyard/src/main/scala/clocking/ClockGroupNamePrefixer.scala

@@ -28,6 +28,7 @@ class ClockGroupParameterModifier(
     sinkFn:   ClockGroupSinkParameters   => ClockGroupSinkParameters   = { s => s })(
     implicit p: Parameters, v: ValName) extends LazyModule {
   val node = ClockGroupAdapterNode(sourceFn, sinkFn)
+  override def shouldBeInlined = true
   lazy val module = new LazyRawModuleImp(this) {
     (node.out zip node.in).map { case ((o, _), (i, _)) =>
       (o.member.data zip i.member.data).foreach { case (oD, iD) => oD := iD }

generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala

@@ -37,9 +37,10 @@ trait HasChipyardPRCI { this: BaseSubsystem with InstantiatesHierarchicalElement
 
   // Set up clock domain
   private val tlbus = locateTLBusWrapper(prciParams.slaveWhere)
-  val prci_ctrl_domain = tlbus.generateSynchronousDomain.suggestName("chipyard_prcictrl_domain")
+  val prci_ctrl_domain = tlbus.generateSynchronousDomain("ChipyardPRCICtrl")
+    .suggestName("chipyard_prcictrl_domain")
 
-  val prci_ctrl_bus = Option.when(prciParams.generatePRCIXBar) { prci_ctrl_domain { TLXbar() } }
+  val prci_ctrl_bus = Option.when(prciParams.generatePRCIXBar) { prci_ctrl_domain { TLXbar(nameSuffix = Some("prcibus")) } }
   prci_ctrl_bus.foreach(xbar => tlbus.coupleTo("prci_ctrl") { (xbar
     := TLFIFOFixer(TLFIFOFixer.all)
     := TLBuffer()
@@ -70,13 +71,13 @@ trait HasChipyardPRCI { this: BaseSubsystem with InstantiatesHierarchicalElement
   }
   val tileClockGater     = Option.when(prciParams.enableTileClockGating) { prci_ctrl_domain {
     val clock_gater = LazyModule(new TileClockGater(prciParams.baseAddress + 0x00000, tlbus.beatBytes))
-    clock_gater.tlNode := TLFragmenter(tlbus.beatBytes, tlbus.blockBytes) := prci_ctrl_bus.get
+    clock_gater.tlNode := TLFragmenter(tlbus.beatBytes, tlbus.blockBytes, nameSuffix = Some("TileClockGater")) := prci_ctrl_bus.get
     clock_gater
   } }
   val tileResetSetter    = Option.when(prciParams.enableTileResetSetting) { prci_ctrl_domain {
     val reset_setter = LazyModule(new TileResetSetter(prciParams.baseAddress + 0x10000, tlbus.beatBytes,
       tile_prci_domains.map(_._2.tile_reset_domain.clockNode.portParams(0).name.get).toSeq, Nil))
-    reset_setter.tlNode := TLFragmenter(tlbus.beatBytes, tlbus.blockBytes) := prci_ctrl_bus.get
+    reset_setter.tlNode := TLFragmenter(tlbus.beatBytes, tlbus.blockBytes, nameSuffix = Some("TileResetSetter")) := prci_ctrl_bus.get
     reset_setter
   } }
 

generators/chipyard/src/main/scala/config/AbstractConfig.scala

@@ -59,6 +59,7 @@ class AbstractConfig extends Config(
   new chipyard.iobinders.WithNICIOPunchthrough ++
   new chipyard.iobinders.WithTraceIOPunchthrough ++
   new chipyard.iobinders.WithUARTTSIPunchthrough ++
+  new chipyard.iobinders.WithGCDBusyPunchthrough ++
   new chipyard.iobinders.WithNMITiedOff ++
 
 
@@ -122,7 +123,6 @@ class AbstractConfig extends Config(
   new freechips.rocketchip.subsystem.WithCoherentBusTopology ++     /** hierarchical buses including sbus/mbus/pbus/fbus/cbus/l2 */
   new chipyard.config.WithSV48IfPossible ++                         /** use sv48 if possible */
 
-
   // ================================================
   //   Set up power, reset and clocking
   // ================================================

generators/chipyard/src/main/scala/config/ClockingConfigs.scala

@@ -0,0 +1,34 @@
+package chipyard
+
+import org.chipsalliance.cde.config.{Config}
+import freechips.rocketchip.diplomacy._
+import freechips.rocketchip.subsystem.{MBUS, SBUS}
+import testchipip.soc.{OBUS}
+
+//==================================================
+// This file contains examples of the different ways
+// clocks can be generated for chiypard designs
+//==================================================
+
+// The default constructs IOs for all requested clocks in the chiptopClockGroupsNode
+// Note: This is what designs inheriting from AbstractConfig do by default
+class DefaultClockingRocketConfig extends Config(
+  new chipyard.clocking.WithPassthroughClockGenerator ++
+  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new chipyard.config.AbstractConfig)
+
+// This is a more physically realistic approach, normally we can't punch out a separate
+// pin for each clock domain. The standard "test chip" approach is to punch a few slow clock
+// inputs, integrate a PLL, and generate an array of selectors/dividers to configure the
+// clocks for each domain. See the source for WithPLLSelectorDividerClockGenerator for more info
+class ChipLikeClockingRocketConfig extends Config(
+  new chipyard.clocking.WithPLLSelectorDividerClockGenerator ++
+  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new chipyard.config.AbstractConfig)
+
+// This merges all the clock domains in chiptopClockGroupsNode into one, then generates a single
+// clock input pin.
+class SingleClockBroadcastRocketConfig extends Config(
+  new chipyard.clocking.WithSingleClockBroadcastClockGenerator ++
+  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new chipyard.config.AbstractConfig)

generators/chipyard/src/main/scala/config/MMIOAcceleratorConfigs.scala

@@ -1,7 +1,6 @@
 package chipyard
 
 import org.chipsalliance.cde.config.{Config}
-import freechips.rocketchip.diplomacy.{AsynchronousCrossing}
 
 // ------------------------------
 // Configs with MMIO accelerators

generators/chipyard/src/main/scala/config/MemorySystemConfigs.scala

@@ -1,7 +1,6 @@
 package chipyard
 
 import org.chipsalliance.cde.config.{Config}
-import freechips.rocketchip.diplomacy.{AsynchronousCrossing}
 
 // ------------------------------------------------------------
 // Configs which demonstrate modifying the uncore memory system

generators/chipyard/src/main/scala/config/NoCConfigs.scala

@@ -1,7 +1,6 @@
 package chipyard
 
 import org.chipsalliance.cde.config.{Config}
-import freechips.rocketchip.diplomacy.{AsynchronousCrossing}
 import freechips.rocketchip.subsystem.{SBUS, MBUS}
 
 import constellation.channel._
@@ -267,3 +266,26 @@ class SbusMeshNoCConfig extends Config(
   new chipyard.config.AbstractConfig
 )
 
+class QuadRocketSbusRingNoCConfig extends Config(
+  new constellation.soc.WithSbusNoC(constellation.protocol.SimpleTLNoCParams(
+    constellation.protocol.DiplomaticNetworkNodeMapping(
+      inNodeMapping = ListMap(
+        "Core 0 " -> 0,
+        "Core 1 " -> 1,
+        "Core 2 " -> 2,
+        "Core 3 " -> 3,
+        "serial_tl" -> 4),
+      outNodeMapping = ListMap(
+        "system[0]" -> 5,
+        "system[1]" -> 6,
+        "system[2]" -> 7,
+        "system[3]" -> 8,
+        "pbus" -> 4)), // TSI is on the pbus, so serial-tl and pbus should be on the same node
+    nocParams = NoCParams(
+      topology        = UnidirectionalTorus1D(9),
+      channelParamGen = (a, b) => UserChannelParams(Seq.fill(10) { UserVirtualChannelParams(4) }),
+      routingRelation = NonblockingVirtualSubnetworksRouting(UnidirectionalTorus1DDatelineRouting(), 5, 2))
+  )) ++
+  new freechips.rocketchip.subsystem.WithNBigCores(4) ++
+  new freechips.rocketchip.subsystem.WithNBanks(4) ++
+  new chipyard.config.AbstractConfig)

generators/chipyard/src/main/scala/config/NoCoreConfigs.scala

@@ -13,9 +13,9 @@ class NoCoresConfig extends Config(
   new chipyard.config.WithNoUART ++
   new chipyard.config.WithNoTileClockGaters ++
   new chipyard.config.WithNoTileResetSetters ++
-  new chipyard.config.WithNoBusErrorDevices ++
   new chipyard.config.WithNoDebug ++
   new chipyard.config.WithNoPLIC ++
+  new chipyard.config.WithNoBusErrorDevices ++
   new chipyard.config.AbstractConfig)
 
 // A config that uses a empty chiptop module with no rocket-chip soc components

generators/chipyard/src/main/scala/config/PeripheralDeviceConfigs.scala

@@ -1,7 +1,6 @@
 package chipyard
 
 import org.chipsalliance.cde.config.{Config}
-import freechips.rocketchip.diplomacy.{AsynchronousCrossing}
 import freechips.rocketchip.subsystem.{MBUS}
 
 // ---------------------------------------------------------

generators/chipyard/src/main/scala/config/RoCCAcceleratorConfigs.scala

@@ -1,7 +1,6 @@
 package chipyard
 
 import org.chipsalliance.cde.config.{Config}
-import freechips.rocketchip.diplomacy.{AsynchronousCrossing}
 
 // ------------------------------
 // Configs with RoCC Accelerators
@@ -48,3 +47,27 @@ class AES256ECBRocketConfig extends Config(
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++
   new chipyard.config.WithSystemBusWidth(256) ++
   new chipyard.config.AbstractConfig)
+
+class ReRoCCTestConfig extends Config(
+  new rerocc.WithReRoCC ++
+  new chipyard.config.WithCharacterCountRoCC ++                // rerocc tile4 is charcnt
+  new chipyard.config.WithAccumulatorRoCC ++                   // rerocc tile3 is accum
+  new chipyard.config.WithAccumulatorRoCC ++                   // rerocc tile2 is accum
+  new chipyard.config.WithAccumulatorRoCC ++                   // rerocc tile1 is accum
+  new chipyard.config.WithAccumulatorRoCC ++                   // rerocc tile0 is accum
+  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new chipyard.config.AbstractConfig)
+
+class ReRoCCManyGemminiConfig extends Config(
+  new rerocc.WithReRoCC ++
+  new gemmini.LeanGemminiConfig ++                              // rerocc tile3 is gemmini
+  new gemmini.LeanGemminiConfig ++                              // rerocc tile2 is gemmini
+  new gemmini.LeanGemminiConfig ++                              // rerocc tile1 is gemmini
+  new gemmini.LeanGemminiConfig ++                              // rerocc tile0 is gemmini
+  new freechips.rocketchip.subsystem.WithNBigCores(4) ++        // 4 rocket cores
+  new chipyard.config.AbstractConfig)
+
+class ZstdCompressorRocketConfig extends Config(
+  new compressacc.WithZstdCompressor ++
+  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new chipyard.config.AbstractConfig)

generators/chipyard/src/main/scala/config/RocketConfigs.scala

@@ -1,7 +1,7 @@
 package chipyard
 
 import org.chipsalliance.cde.config.{Config}
-import freechips.rocketchip.diplomacy.{AsynchronousCrossing}
+import freechips.rocketchip.prci.{AsynchronousCrossing}
 import freechips.rocketchip.subsystem.{InCluster}
 
 // --------------
@@ -12,6 +12,10 @@ class RocketConfig extends Config(
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++         // single rocket-core
   new chipyard.config.AbstractConfig)
 
+class DualRocketConfig extends Config(
+  new freechips.rocketchip.subsystem.WithNBigCores(2) ++
+  new chipyard.config.AbstractConfig)
+
 class TinyRocketConfig extends Config(
   new chipyard.harness.WithDontTouchChipTopPorts(false) ++        // TODO FIX: Don't dontTouch the ports
   new testchipip.soc.WithNoScratchpads ++                         // All memory is the Rocket TCMs

generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala

@@ -7,7 +7,7 @@ import chisel3.util.{log2Up}
 import org.chipsalliance.cde.config.{Config}
 import freechips.rocketchip.devices.tilelink.{BootROMLocated, PLICKey, CLINTKey}
 import freechips.rocketchip.devices.debug.{Debug, ExportDebug, DebugModuleKey, DMI, JtagDTMKey, JtagDTMConfig}
-import freechips.rocketchip.diplomacy.{AsynchronousCrossing}
+import freechips.rocketchip.prci.{AsynchronousCrossing}
 import chipyard.stage.phases.TargetDirKey
 import freechips.rocketchip.subsystem._
 import freechips.rocketchip.tile.{XLen}

generators/chipyard/src/main/scala/config/fragments/RoCCFragments.scala

@@ -43,3 +43,17 @@ class WithMultiRoCCGemmini[T <: Data : Arithmetic, U <: Data, V <: Data](
     }))
   }
 })
+
+class WithAccumulatorRoCC(op: OpcodeSet = OpcodeSet.custom1) extends Config((site, here, up) => {
+  case BuildRoCC => up(BuildRoCC) ++ Seq((p: Parameters) => {
+    val accumulator = LazyModule(new AccumulatorExample(op, n = 4)(p))
+    accumulator
+  })
+})
+
+class WithCharacterCountRoCC(op: OpcodeSet = OpcodeSet.custom2) extends Config((site, here, up) => {
+  case BuildRoCC => up(BuildRoCC) ++ Seq((p: Parameters) => {
+    val counter = LazyModule(new CharacterCountExample(op)(p))
+    counter
+  })
+})

generators/chipyard/src/main/scala/config/fragments/SubsystemFragments.scala

@@ -2,7 +2,7 @@ package chipyard.config
 
 import org.chipsalliance.cde.config.{Config}
 import freechips.rocketchip.subsystem._
-import freechips.rocketchip.diplomacy.{DTSTimebase}
+import freechips.rocketchip.resources.{DTSTimebase}
 import sifive.blocks.inclusivecache.{InclusiveCachePortParameters}
 
 // Replaces the L2 with a broadcast manager for maintaining coherence

generators/chipyard/src/main/scala/example/TutorialTile.scala

@@ -14,7 +14,7 @@ import freechips.rocketchip.interrupts._
 import freechips.rocketchip.util._
 import freechips.rocketchip.tile._
 import freechips.rocketchip.amba.axi4._
-import freechips.rocketchip.prci.ClockSinkParameters
+import freechips.rocketchip.prci._
 
 // Example parameter class copied from CVA6, not included in documentation but for compile check only
 // If you are here for documentation, DO NOT copy MyCoreParams and MyTileParams directly - always figure

generators/chipyard/src/main/scala/iobinders/IOBinders.scala

@@ -39,6 +39,7 @@ import testchipip.cosim.{CanHaveTraceIO, TraceOutputTop, SpikeCosimConfig}
 import testchipip.tsi.{CanHavePeripheryUARTTSI, UARTTSIIO}
 import icenet.{CanHavePeripheryIceNIC, SimNetwork, NicLoopback, NICKey, NICIOvonly}
 import chipyard.{CanHaveMasterTLMemPort, HasCeaseIO, ChipyardSystem, ChipyardSystemModule}
+import chipyard.example.{CanHavePeripheryGCD}
 
 import scala.reflect.{ClassTag}
 
@@ -548,3 +549,11 @@ class WithNMITiedOff extends ComposeIOBinder({
     (Nil, Nil)
   }
 })
+
+class WithGCDBusyPunchthrough extends OverrideIOBinder({
+  (system: CanHavePeripheryGCD) => system.gcd_busy.map { busy =>
+    val io_gcd_busy = IO(Output(Bool()))
+    io_gcd_busy := busy
+    (Seq(GCDBusyPort(() => io_gcd_busy)), Nil)
+  }.getOrElse((Nil, Nil))
+})

generators/chipyard/src/main/scala/iobinders/Ports.scala

@@ -109,3 +109,5 @@ case class JTAGResetPort   (val getIO: () => Reset)
 case class TLMemPort       (val getIO: () => HeterogeneousBag[TLBundle])
     extends Port[HeterogeneousBag[TLBundle]]
 
+case class GCDBusyPort     (val getIO: () => Bool)
+    extends Port[Bool]

generators/firechip/src/main/scala/TargetConfigs.scala

@@ -12,7 +12,8 @@ import freechips.rocketchip.rocket.DCacheParams
 import freechips.rocketchip.subsystem._
 import freechips.rocketchip.devices.tilelink.{BootROMLocated, BootROMParams}
 import freechips.rocketchip.devices.debug.{DebugModuleParams, DebugModuleKey}
-import freechips.rocketchip.diplomacy.{LazyModule, AsynchronousCrossing}
+import freechips.rocketchip.diplomacy.{LazyModule}
+import freechips.rocketchip.prci.{AsynchronousCrossing}
 import testchipip.iceblk.{BlockDeviceKey, BlockDeviceConfig}
 import testchipip.cosim.{TracePortKey, TracePortParams}
 import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams}
@@ -368,6 +369,12 @@ class FireSimRadianceClusterSynConfig extends Config(
   new WithFireSimConfigTweaks ++
   new chipyard.RadianceClusterSynConfig)
 
+class FireSimQuadRocketSbusRingNoCConfig extends Config(
+  new chipyard.config.WithNoTraceIO ++
+  new WithDefaultFireSimBridges ++
+  new WithFireSimConfigTweaks++
+  new chipyard.QuadRocketSbusRingNoCConfig)
+
 class FireSimLargeBoomSV39CospikeConfig extends Config(
   new firesim.firesim.WithCospikeBridge ++
   new WithDefaultFireSimBridges ++