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Correctly support reset for spiketile

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This commit is contained in:
Jerry Zhao
2023-01-06 16:53:20 -08:00
parent 2a08ca9c70
commit 2badb7e3f6
2 changed files with 10 additions and 1 deletions
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7
generators/chipyard/src/main/resources/csrc/spiketile.cc
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@@ -150,6 +150,13 @@ std::map<int, tile_t*> tiles;
std::ostream sout(nullptr); std::ostream sout(nullptr);
log_file_t* log_file; log_file_t* log_file;
extern "C" void spike_tile_reset(int hartid)
{
if (tiles.find(hartid) != tiles.end()) {
tiles[hartid]->proc->reset();
}
}
extern "C" void spike_tile(int hartid, char* isa, extern "C" void spike_tile(int hartid, char* isa,
int pmpregions, int pmpregions,
int icache_sets, int icache_ways, int icache_sets, int icache_ways,

4
generators/chipyard/src/main/resources/vsrc/spiketile.v
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@@ -1,3 +1,5 @@
import "DPI-C" function void spike_tile_reset(input int hartid);
import "DPI-C" function void spike_tile(input int hartid, import "DPI-C" function void spike_tile(input int hartid,
input string isa, input string isa,
input int pmpregions, input int pmpregions,
@@ -320,7 +322,7 @@ module SpikeBlackBox #(
__dcache_c_data_6_reg <= 64'h0; __dcache_c_data_6_reg <= 64'h0;
__dcache_c_data_7 = 64'h0; __dcache_c_data_7 = 64'h0;
__dcache_c_data_7_reg <= 64'h0; __dcache_c_data_7_reg <= 64'h0;
spike_tile_reset(HARTID);
end else begin end else begin
spike_tile(HARTID, ISA, PMPREGIONS, spike_tile(HARTID, ISA, PMPREGIONS,
ICACHE_SETS, ICACHE_WAYS, DCACHE_SETS, DCACHE_WAYS, ICACHE_SETS, ICACHE_WAYS, DCACHE_SETS, DCACHE_WAYS,