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Cleanup config + fragments | Remove reference clk div/rst catch in harness [ci skip]

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This commit is contained in:
abejgonzalez
2021-03-05 12:25:59 -08:00
parent 60a616e320
commit 2b7e359326
4 changed files with 30 additions and 20 deletions
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9
generators/chipyard/src/main/scala/ConfigFragments.scala
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@@ -205,8 +205,13 @@ class WithSerialTLBackingMemory extends Config((site, here, up) => {
)} )}
}) })
class WithTileFrequency(fMHz: Double) extends ClockNameContainsAssignment("tile", fMHz) class WithTileFrequency(fMHz: Double, hartId: Option[Int] = None) extends ClockNameContainsAssignment({
class WithSpecificTileFrequency(hartId: Int, fMHz: Double) extends chipyard.ClockNameContainsAssignment(s"tile_$hartId", fMHz) hartId match {
case Some(id) => s"tile_$id"
case None => "tile"
}
},
fMHz)
class WithPeripheryBusFrequencyAsDefault extends Config((site, here, up) => { class WithPeripheryBusFrequencyAsDefault extends Config((site, here, up) => {
case DefaultClockFrequencyKey => (site(PeripheryBusKey).dtsFrequency.get / (1000 * 1000)).toDouble case DefaultClockFrequencyKey => (site(PeripheryBusKey).dtsFrequency.get / (1000 * 1000)).toDouble

4
generators/chipyard/src/main/scala/HarnessBinders.scala
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@@ -83,9 +83,7 @@ class WithGPIOTiedOff extends OverrideHarnessBinder({
// DOC include start: WithUARTAdapter // DOC include start: WithUARTAdapter
class WithUARTAdapter extends OverrideHarnessBinder({ class WithUARTAdapter extends OverrideHarnessBinder({
(system: HasPeripheryUARTModuleImp, th: HasHarnessSignalReferences, ports: Seq[UARTPortIO]) => { (system: HasPeripheryUARTModuleImp, th: HasHarnessSignalReferences, ports: Seq[UARTPortIO]) => {
withClockAndReset(th.harnessClock, th.harnessReset) { UARTAdapter.connect(ports)(system.p)
UARTAdapter.connect(ports)(system.p)
}
} }
}) })
// DOC include end: WithUARTAdapter // DOC include end: WithUARTAdapter

14
generators/chipyard/src/main/scala/TestHarness.scala
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@@ -57,13 +57,19 @@ class HarnessClockInstantiator {
divider.io.clk_out divider.io.clk_out
} }
// TODO: on the implicit clock just create a passthrough (don't instantiate a divider + reset catch)
// connect wires to clock source // connect wires to clock source
for (sinkParams <- sinks) { for (sinkParams <- sinks) {
val div = pllConfig.sinkDividerMap(sinkParams) // bypass the reference freq. (don't create a divider + reset sync)
val divClock = dividedClocks.getOrElse(div, instantiateDivider(div)) val (divClock, divReset) = if (sinkParams.take.get.freqMHz != pllConfig.referenceFreqMHz) {
val div = pllConfig.sinkDividerMap(sinkParams)
val divClock = dividedClocks.getOrElse(div, instantiateDivider(div))
(divClock, ResetCatchAndSync(divClock, refClock.reset.asBool))
} else {
(refClock.clock, refClock.reset)
}
_clockMap(sinkParams.name.get)._2.clock := divClock _clockMap(sinkParams.name.get)._2.clock := divClock
_clockMap(sinkParams.name.get)._2.reset := ResetCatchAndSync(divClock, refClock.reset.asBool) _clockMap(sinkParams.name.get)._2.reset := divReset
} }
} }
} }

23
generators/chipyard/src/main/scala/config/RocketConfigs.scala
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@@ -1,8 +1,7 @@
package chipyard package chipyard
import freechips.rocketchip.config.{Config} import freechips.rocketchip.config.{Config}
import freechips.rocketchip.diplomacy.{AsynchronousCrossing, RationalCrossing} import freechips.rocketchip.diplomacy.{AsynchronousCrossing}
import freechips.rocketchip.util.{SlowToFast}
// -------------- // --------------
// Rocket Configs // Rocket Configs
@@ -215,20 +214,22 @@ class LBWIFRocketConfig extends Config(
new chipyard.config.AbstractConfig) new chipyard.config.AbstractConfig)
class MulticlockAXIOverSerialConfig extends Config( class MulticlockAXIOverSerialConfig extends Config(
new chipyard.config.WithFbusToSbusCrossingType(RationalCrossing(SlowToFast)) ++
new chipyard.config.WithSystemBusFrequencyAsDefault ++ new chipyard.config.WithSystemBusFrequencyAsDefault ++
new chipyard.config.WithSystemBusFrequency(4000) ++ new chipyard.config.WithSystemBusFrequency(500) ++
new chipyard.config.WithPeripheryBusFrequency(4000) ++ new chipyard.config.WithPeripheryBusFrequency(500) ++
new chipyard.config.WithMemoryBusFrequency(4000) ++ new chipyard.config.WithMemoryBusFrequency(500) ++
new chipyard.config.WithFrontBusFrequency(50) ++
new chipyard.config.WithTileFrequency(1000, Some(1)) ++
new chipyard.config.WithTileFrequency(250, Some(0)) ++
new chipyard.config.WithFrontBusFrequency(4000 / 2) ++ new chipyard.config.WithFbusToSbusCrossingType(AsynchronousCrossing()) ++
new chipyard.config.WithFbusToSbusCrossingType(RationalCrossing(SlowToFast)) ++
new testchipip.WithAsynchronousSerialSlaveCrossing ++ new testchipip.WithAsynchronousSerialSlaveCrossing ++
new freechips.rocketchip.subsystem.WithAsynchronousRocketTiles(
AsynchronousCrossing().depth,
AsynchronousCrossing().sourceSync) ++
new chipyard.harness.WithSimAXIMemOverSerialTL ++ // add SimDRAM DRAM model for axi4 backing memory over the SerDes link, if axi4 mem is enabled new chipyard.harness.WithSimAXIMemOverSerialTL ++ // add SimDRAM DRAM model for axi4 backing memory over the SerDes link, if axi4 mem is enabled
new chipyard.config.WithSerialTLBackingMemory ++ // remove axi4 mem port in favor of SerialTL memory new chipyard.config.WithSerialTLBackingMemory ++ // remove axi4 mem port in favor of SerialTL memory
new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new freechips.rocketchip.subsystem.WithNBigCores(2) ++
new chipyard.config.AbstractConfig) new chipyard.config.AbstractConfig)