Use ProjectRef for FIRRTL and use it for firrtl-interpreter
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@@ -81,9 +81,12 @@ def isolateAllTests(tests: Seq[TestDefinition]) = tests map { test =>
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// Subproject definitions begin
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// Subproject definitions begin
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lazy val chisel = (project in file("tools/chisel3"))
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lazy val chisel = (project in file("tools/chisel3"))
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lazy val firrtl = ProjectRef(workspaceDirectory / "firrtl", "firrtl")
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lazy val firrtl_interpreter = (project in file("tools/firrtl-interpreter"))
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lazy val firrtl_interpreter = (project in file("tools/firrtl-interpreter"))
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.dependsOn(firrtl)
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.settings(commonSettings)
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.settings(commonSettings)
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lazy val treadle = (project in file("tools/treadle"))
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lazy val treadle = (project in file("tools/treadle"))
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@@ -107,7 +110,8 @@ lazy val midasTargetUtils = ProjectRef(firesimDir, "targetutils")
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// Rocket-chip dependencies (subsumes making RC a RootProject)
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// Rocket-chip dependencies (subsumes making RC a RootProject)
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lazy val hardfloat = (project in rocketChipDir / "hardfloat")
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lazy val hardfloat = (project in rocketChipDir / "hardfloat")
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.settings(commonSettings).dependsOn(midasTargetUtils)
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.dependsOn(midasTargetUtils)
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.settings(commonSettings)
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lazy val rocketMacros = (project in rocketChipDir / "macros")
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lazy val rocketMacros = (project in rocketChipDir / "macros")
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.settings(commonSettings)
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.settings(commonSettings)
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