From 4adb8d91c1382c58865e413a5a358703a7e95a8a Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Tue, 11 Apr 2023 17:44:24 -0700 Subject: [PATCH 1/4] Fix ChipLikeQuadRocketConfig crossing There needs to be a crossing between sbus/fbus when they are on separate clock domains --- generators/chipyard/src/main/scala/config/ChipConfigs.scala | 1 + 1 file changed, 1 insertion(+) diff --git a/generators/chipyard/src/main/scala/config/ChipConfigs.scala b/generators/chipyard/src/main/scala/config/ChipConfigs.scala index 7f875584..fa08acf7 100644 --- a/generators/chipyard/src/main/scala/config/ChipConfigs.scala +++ b/generators/chipyard/src/main/scala/config/ChipConfigs.scala @@ -35,6 +35,7 @@ class ChipLikeQuadRocketConfig extends Config( new chipyard.clocking.WithClockGroupsCombinedByName("fbus", "fbus", "pbus") ++ // Set up the crossings + new chipyard.config.WithFbusToSbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossing between SBUS and FBUS new chipyard.config.WithCbusToPbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossing between PBUS and CBUS new chipyard.config.WithSbusToMbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossings between backside of L2 and MBUS new testchipip.WithAsynchronousSerialSlaveCrossing ++ // Add Async crossing between serial and MBUS. Its master-side is tied to the FBUS From 344e29a240628e866ce24e81dc29c0ea0887d719 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Wed, 12 Apr 2023 11:59:57 -0700 Subject: [PATCH 2/4] Switch ChipLikequadRocketConfig to use the FlatTestHarness in CI --- .github/scripts/defaults.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/scripts/defaults.sh b/.github/scripts/defaults.sh index 13bcf116..83117317 100755 --- a/.github/scripts/defaults.sh +++ b/.github/scripts/defaults.sh @@ -53,7 +53,7 @@ mapping["chipyard-cva6"]=" CONFIG=CVA6Config" mapping["chipyard-ibex"]=" CONFIG=IbexConfig" mapping["chipyard-spiflashwrite"]=" CONFIG=SmallSPIFlashRocketConfig EXTRA_SIM_FLAGS='+spiflash0=${LOCAL_CHIPYARD_DIR}/tests/spiflash.img'" mapping["chipyard-manyperipherals"]=" CONFIG=ManyPeripheralsRocketConfig EXTRA_SIM_FLAGS='+spiflash0=${LOCAL_CHIPYARD_DIR}/tests/spiflash.img'" -mapping["chipyard-chiplike"]=" CONFIG=ChipLikeQuadRocketConfig verilog" +mapping["chipyard-chiplike"]=" CONFIG=ChipLikeQuadRocketConfig MODEL=FlatTestHarness MODEL_PACKAGE=chipyard.example verilog" mapping["chipyard-cloneboom"]=" CONFIG=Cloned64MegaBoomConfig verilog" mapping["chipyard-nocores"]=" CONFIG=NoCoresConfig verilog" mapping["tracegen"]=" CONFIG=NonBlockingTraceGenL2Config" From 8c78effdf466eeb0d2c09e42d27117e29209e5d2 Mon Sep 17 00:00:00 2001 From: "-T.K.-" Date: Wed, 12 Apr 2023 21:53:53 -0700 Subject: [PATCH 3/4] ADD: improve variable definition, add explicit arch flags --- tests/Makefile | 52 ++++++++++++++++++++++++++++++++++++++++---------- 1 file changed, 42 insertions(+), 10 deletions(-) diff --git a/tests/Makefile b/tests/Makefile index 8756350d..5628aeac 100644 --- a/tests/Makefile +++ b/tests/Makefile @@ -1,7 +1,29 @@ -GCC=riscv64-unknown-elf-gcc -OBJDUMP=riscv64-unknown-elf-objdump -CFLAGS= -std=gnu99 -O2 -fno-common -fno-builtin-printf -Wall -LDFLAGS= -static +################################# +# RISCV Toolchain +################################# + +PREFIX = riscv64-unknown-elf- + +GCC = $(PREFIX)gcc +CXX = $(PREFIX)g++ +CP = $(PREFIX)objcopy +OBJDUMP = $(PREFIX)objdump +DG = $(PREFIX)gdb +SIZE = $(PREFIX)size + + +################################# +# Flags +################################# + +# SoC Settings +ARCH = rv64imafdc +ABI = lp64d +ARCHFLAGS = -march=$(ARCH) -mabi=$(ABI) + +CFLAGS = -std=gnu99 -O2 -fno-common -fno-builtin-printf -Wall +CFLAGS += $(ARCHFLAGS) +LDFLAGS = -static include libgloss.mk @@ -9,16 +31,16 @@ PROGRAMS = pwm blkdev accum charcount nic-loopback big-blkdev pingd \ streaming-passthrough streaming-fir nvdla spiflashread spiflashwrite fft gcd \ hello -spiflash.img: spiflash.py - python3 $< .DEFAULT_GOAL := default -.PHONY: default -default: $(addsuffix .riscv,$(PROGRAMS)) spiflash.img -.PHONY: dumps -dumps: $(addsuffix .dump,$(PROGRAMS)) +################################# +# Build +################################# + +spiflash.img: spiflash.py + python3 $< %.o: %.S $(GCC) $(CFLAGS) -D__ASSEMBLY__=1 -c $< -o $@ @@ -33,7 +55,17 @@ dumps: $(addsuffix .dump,$(PROGRAMS)) $(OBJDUMP) -D $< > $@ +################################# +# Recipes +################################# + .PHONY: clean clean: rm -f *.riscv *.o *.dump $(if $(libgloss),rm -rf $(libgloss_builddir)/) + +.PHONY: default +default: $(addsuffix .riscv, $(PROGRAMS)) spiflash.img + +.PHONY: dumps +dumps: $(addsuffix .dump, $(PROGRAMS)) From ad9ea333d1dfa8f6cef4da5401eb086a42dffb94 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Mon, 10 Apr 2023 15:35:53 -0700 Subject: [PATCH 4/4] Bump TestChipIp to improve default serial_tl behavior --- generators/chipyard/src/main/scala/config/ChipConfigs.scala | 1 - generators/testchipip | 2 +- 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/generators/chipyard/src/main/scala/config/ChipConfigs.scala b/generators/chipyard/src/main/scala/config/ChipConfigs.scala index fa08acf7..2d6cb206 100644 --- a/generators/chipyard/src/main/scala/config/ChipConfigs.scala +++ b/generators/chipyard/src/main/scala/config/ChipConfigs.scala @@ -39,7 +39,6 @@ class ChipLikeQuadRocketConfig extends Config( new chipyard.config.WithCbusToPbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossing between PBUS and CBUS new chipyard.config.WithSbusToMbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossings between backside of L2 and MBUS new testchipip.WithAsynchronousSerialSlaveCrossing ++ // Add Async crossing between serial and MBUS. Its master-side is tied to the FBUS - new testchipip.WithSerialTLAsyncResetQueue ++ // Add Async reset queue to block ready while in reset new chipyard.config.AbstractConfig) diff --git a/generators/testchipip b/generators/testchipip index aa9170af..0d943d04 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit aa9170afe133e74e1c66b0082dc943e272d9e6f0 +Subproject commit 0d943d04b5510a3ee86f5145db6a4de80987bc5e