diff --git a/README.md b/README.md index 5d44edb3..c2feb678 100644 --- a/README.md +++ b/README.md @@ -29,13 +29,28 @@ Chipyard is actively developed in the [Berkeley Architecture Research Group][ucb * See [CONTRIBUTING.md](/CONTRIBUTING.md) -## Chipyard-related Publications +## Attribution and Chipyard-related Publications -These publications cover many of the internal components used in Chipyard. However, for the most up-to-date details, users should refer to the Chipyard docs. +If used for research, please cite Chipyard by the following publication: + +``` +@article{chipyard, + author={Amid, Alon and Biancolin, David and Gonzalez, Abraham and Grubb, Daniel and Karandikar, Sagar and Liew, Harrison and Magyar, Albert and Mao, Howard and Ou, Albert and Pemberton, Nathan and Rigge, Paul and Schmidt, Colin and Wright, John and Zhao, Jerry and Shao, Yakun Sophia and Asanovi\'{c}, Krste and Nikoli\'{c}, Borivoje}, + journal={IEEE Micro}, + title={Chipyard: Integrated Design, Simulation, and Implementation Framework for Custom SoCs}, + year={2020}, + pages={}, + doi={10.1109/MM.2020.2996616}, + ISSN={1937-4143}, +} +``` + +These additional publications cover many of the internal components used in Chipyard. However, for the most up-to-date details, users should refer to the Chipyard docs. * **Generators** * **Rocket Chip**: K. Asanovic, et al., *UCB EECS TR*. [PDF](http://www2.eecs.berkeley.edu/Pubs/TechRpts/2016/EECS-2016-17.pdf). * **BOOM**: C. Celio, et al., *Hot Chips 30*. [PDF](https://www.hotchips.org/hc30/1conf/1.03_Berkeley_BROOM_HC30.Berkeley.Celio.v02.pdf). + * **SonicBOOM (BOOMv3): J. Zhao, et al., *CARRV'20*. [PDF](https://carrv.github.io/2020/papers/CARRV2020_paper_15_Zhao.pdf). * **Hwacha**: Y. Lee, et al., *ESSCIRC'14*. [PDF](http://hwacha.org/papers/riscv-esscirc2014.pdf). * **Gemmini**: H. Genc, et al., *arXiv*. [PDF](https://arxiv.org/pdf/1911.09925). * **Sims** diff --git a/docs/Customization/Memory-Hierarchy.rst b/docs/Customization/Memory-Hierarchy.rst index 733e70c6..554b6d5f 100644 --- a/docs/Customization/Memory-Hierarchy.rst +++ b/docs/Customization/Memory-Hierarchy.rst @@ -31,8 +31,8 @@ Note that these configurations fully remove the L2 cache and mbus. .. literalinclude:: ../../generators/chipyard/src/main/scala/config/RocketConfigs.scala :language: scala - :start-after: DOC include start: scratchpadrocket - :end-before: DOC include end: scratchpadrocket + :start-after: DOC include start: l1scratchpadrocket + :end-before: DOC include end: l1scratchpadrocket This configuration fully removes the L2 cache and memory bus by setting the @@ -94,11 +94,20 @@ number of DRAM channels is restricted to powers of two. new freechips.rocketchip.subsystem.WithNMemoryChannels(2) - In VCS and Verilator simulation, the DRAM is simulated using the ``SimAXIMem`` module, which simply attaches a single-cycle SRAM to each memory channel. +Instead of connecting to off-chip DRAM, you can instead connect a scratchpad +and remove the off-chip link. This is done by adding a fragment like +``testchipip.WithBackingScratchpad`` to your configuration and removing the +memory port with ``freechips.rocketchip.subsystem.WithNoMemPort``. + +.. literalinclude:: ../../generators/chipyard/src/main/scala/config/RocketConfigs.scala + :language: scala + :start-after: DOC include start: mbusscratchpadrocket + :end-before: DOC include end: mbusscratchpadrocket + If you want a more realistic memory simulation, you can use FireSim, which can simulate the timing of DDR3 controllers. More documentation on FireSim memory models is available in the `FireSim docs `_. diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala index f29c5804..32077ad8 100644 --- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala +++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala @@ -384,14 +384,35 @@ class LoopbackNICRocketConfig extends Config( new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) -// DOC include start: scratchpadrocket -class ScratchpadRocketConfig extends Config( +// DOC include start: l1scratchpadrocket +class L1ScratchpadSmallRocketConfig extends Config( new chipyard.iobinders.WithUARTAdapter ++ new chipyard.iobinders.WithTieOffInterrupts ++ new chipyard.iobinders.WithTiedOffDebug ++ new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ - new testchipip.WithBackingScratchpad ++ // add backing scratchpad + new chipyard.config.WithBootROM ++ + new chipyard.config.WithUART ++ + new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ // remove offchip mem port + new freechips.rocketchip.subsystem.WithNBanks(0) ++ + new freechips.rocketchip.subsystem.WithNoMemPort ++ + new freechips.rocketchip.subsystem.WithNoMMIOPort ++ + new freechips.rocketchip.subsystem.WithNoSlavePort ++ + new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use rocket l1 scratchpad + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ + new freechips.rocketchip.subsystem.WithNSmallCores(1) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ + new freechips.rocketchip.system.BaseConfig) +// DOC include end: l1scratchpadrocket + +// DOC include start: mbusscratchpadrocket +class MbusScratchpadRocketConfig extends Config( + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimSerial ++ + new testchipip.WithTSI ++ + new testchipip.WithBackingScratchpad ++ // add mbus backing scratchpad new chipyard.config.WithBootROM ++ new chipyard.config.WithUART ++ new chipyard.config.WithL2TLBs(1024) ++ @@ -403,7 +424,7 @@ class ScratchpadRocketConfig extends Config( new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) -// DOC include end: scratchpadrocket +// DOC include end: mbusscratchpadrocket // DOC include start: RingSystemBusRocket class RingSystemBusRocketConfig extends Config( diff --git a/generators/utilities/src/main/resources/csrc/emulator.cc b/generators/utilities/src/main/resources/csrc/emulator.cc index 6ff63d3e..1a5a7ac3 100644 --- a/generators/utilities/src/main/resources/csrc/emulator.cc +++ b/generators/utilities/src/main/resources/csrc/emulator.cc @@ -126,27 +126,30 @@ int main(int argc, char** argv) int verilog_plusargs_legal = 1; dramsim = 0; + opterr = 1; while (1) { static struct option long_options[] = { - {"cycle-count", no_argument, 0, 'c' }, - {"help", no_argument, 0, 'h' }, - {"max-cycles", required_argument, 0, 'm' }, - {"seed", required_argument, 0, 's' }, - {"rbb-port", required_argument, 0, 'r' }, - {"verbose", no_argument, 0, 'V' }, - {"dramsim", no_argument, 0, 'D' }, + {"cycle-count", no_argument, 0, 'c' }, + {"help", no_argument, 0, 'h' }, + {"max-cycles", required_argument, 0, 'm' }, + {"seed", required_argument, 0, 's' }, + {"rbb-port", required_argument, 0, 'r' }, + {"verbose", no_argument, 0, 'V' }, + {"dramsim", no_argument, 0, 'D' }, + {"permissive", no_argument, 0, 'p' }, + {"permissive-off", no_argument, 0, 'o' }, #if VM_TRACE - {"vcd", required_argument, 0, 'v' }, - {"dump-start", required_argument, 0, 'x' }, + {"vcd", required_argument, 0, 'v' }, + {"dump-start", required_argument, 0, 'x' }, #endif HTIF_LONG_OPTIONS }; int option_index = 0; #if VM_TRACE - int c = getopt_long(argc, argv, "-chm:s:r:v:Vx:D", long_options, &option_index); + int c = getopt_long(argc, argv, "-chm:s:r:v:Vx:Dpo", long_options, &option_index); #else - int c = getopt_long(argc, argv, "-chm:s:r:VD", long_options, &option_index); + int c = getopt_long(argc, argv, "-chm:s:r:VDpo", long_options, &option_index); #endif if (c == -1) break; retry: @@ -160,6 +163,8 @@ int main(int argc, char** argv) case 'r': rbb_port = atoi(optarg); break; case 'V': verbose = true; break; case 'D': dramsim = 1; break; + case 'p': opterr = 0; break; + case 'o': opterr = 1; break; #if VM_TRACE case 'v': { vcdfile = strcmp(optarg, "-") == 0 ? stdout : fopen(optarg, "w"); @@ -195,6 +200,10 @@ int main(int argc, char** argv) c = 'c'; else if (arg == "+dramsim") c = 'D'; + else if (arg == "+permissive") + c = 'p'; + else if (arg == "+permissive-off") + c = 'o'; // If we don't find a legacy '+' EMULATOR argument, it still could be // a VERILOG_PLUSARG and not an error. else if (verilog_plusargs_legal) { @@ -226,9 +235,13 @@ int main(int argc, char** argv) } htif_option++; } - std::cerr << argv[0] << ": invalid plus-arg (Verilog or HTIF) \"" - << arg << "\"\n"; - c = '?'; + if(opterr) { + std::cerr << argv[0] << ": invalid plus-arg (Verilog or HTIF) \"" + << arg << "\"\n"; + c = '?'; + } else { + c = 'p'; + } } goto retry; } diff --git a/sims/verilator/Makefile b/sims/verilator/Makefile index 9d99f78c..1b9276ac 100644 --- a/sims/verilator/Makefile +++ b/sims/verilator/Makefile @@ -28,9 +28,6 @@ sim_prefix = simulator sim = $(sim_dir)/$(sim_prefix)-$(MODEL_PACKAGE)-$(CONFIG) sim_debug = $(sim_dir)/$(sim_prefix)-$(MODEL_PACKAGE)-$(CONFIG)-debug -PERMISSIVE_ON= -PERMISSIVE_OFF= - WAVEFORM_FLAG=-v$(sim_out_name).vcd .PHONY: default debug diff --git a/variables.mk b/variables.mk index ad981245..4d49d5fe 100644 --- a/variables.mk +++ b/variables.mk @@ -136,6 +136,8 @@ output_dir=$(sim_dir)/output/$(long_name) ######################################################################################### # helper variables to run binaries ######################################################################################### +PERMISSIVE_ON=+permissive +PERMISSIVE_OFF=+permissive-off BINARY ?= override SIM_FLAGS += +dramsim +max-cycles=$(timeout_cycles) VERBOSE_FLAGS ?= +verbose