move documentation to docs/ and new Makefile plumbing

vlsi/Makefile

@@ -28,12 +28,20 @@ OBJ_DIR            ?= $(vlsi_dir)/build
 ENV_YML            ?= $(vlsi_dir)/bwrc-env.yml
 INPUT_CONFS        ?= example.yml
 HAMMER_EXEC        ?= ./example-vlsi
+VLSI_TOP           ?= $(TOP)
 
 #########################################################################################
 # general rules
 #########################################################################################
-ALL_RTL = $(TOP_FILE) $(TOP_SMEMS_FILE) $(extra_v_includes)
+ALL_RTL = $(TOP_FILE) $(TOP_SMEMS_FILE)
 extra_v_includes = $(build_dir)/EICG_wrapper.v $(vlsi_dir)/example.v
+ifneq ($(CUSTOM_VLOG), )
+	VLSI_RTL = $(CUSTOM_VLOG)
+	VLSI_BB = /dev/null
+else
+	VLSI_RTL = $(ALL_RTL) $(extra_v_includes)
+	VLSI_BB = $(sim_top_blackboxes)
+endif
 
 .PHONY: default verilog
 default: all
@@ -74,14 +82,17 @@ $(SRAM_CONF): $(SRAM_GENERATOR_CONF)
 # synthesis input configuration
 #########################################################################################
 SYN_CONF = $(OBJ_DIR)/inputs.yml
-GENERATED_CONFS = $(SYN_CONF) $(if $(filter $(tech_name), asap7), , $(SRAM_CONF))
+GENERATED_CONFS = $(SYN_CONF)
+ifeq ($(CUSTOM_VLOG), )
+	GENERATED_CONFS += $(if $(filter $(tech_name), asap7), , $(SRAM_CONF))
+endif
 
-$(SYN_CONF): $(ALL_RTL) $(extra_v_includes) $(sim_top_blackboxes)
+$(SYN_CONF): $(VLSI_RTL) $(VLSI_BB)
 	mkdir -p $(dir $@)
 	echo "synthesis.inputs:" > $@
-	echo "  top_module: $(TOP)" >> $@
+	echo "  top_module: $(VLSI_TOP)" >> $@
 	echo "  input_files:" >> $@
-	for x in $(ALL_RTL) $(extra_v_includes) `cat $(sim_top_blackboxes)`; do \
+	for x in $(VLSI_RTL) `cat $(VLSI_BB)`; do \
 		echo '    - "'$$x'"' >> $@; \
 	done
 

vlsi/README.md

@@ -1,72 +0,0 @@
-# HAMMER VLSI flow
-This is the starting point for a vlsi flow from this repository.
-
-This flow will not work without the necessary CAD and technology plugins for HAMMER.
-
-If you are a UCB-affiliate, you may be able to acquire access to the tool & tech plugins.
-
-# Initial Setup Instructions (For all technologies)
-Run the `init-vlsi.sh` script to pull correct versions of hammer, hammer-TOOL\_VENDOR-plugins, and the hammer-TECH\_NAME-plugins. Note the technologies `asap7` and `saed32` are already included and will not submodule a tech plugin.
-```shell
-./scripts/init-vlsi.sh TECH_NAME
-```
-
-An example of tool environment configuration for BWRC affiliates is given in `bwrc-env.yml`. Replace as necessary for your environment.
-
-# Example design
-## Building the design
-In this example, you will be running a SHA-3 accelerator with a dummy hard macro through the VLSI flow in the ASAP7 process. To elaborate the Sha3RocketConfig (Rocketchip w/ the accelerator) and set up all prerequisites for the build system:
-```shell
-export MACROCOMPILER_MODE=' --mode synflops'
-export CONFIG=Sha3RocketConfig
-make buildfile
-```
-Note that because the ASAP7 process does not yet have a memory compiler, synflops are elaborated instead.
-
-## Using HAMMER
-HAMMER's configuration is driven by a JSON/YAML format. For HAMMER, JSON and YAML files are equivalent - you can use either one since HAMMER will convert them to the same representation for itself.
-
-We start by pulling the HAMMER environment into the shell:
-
-```shell
-export HAMMER_HOME=$PWD/hammer
-source $HAMMER_HOME/sourceme.sh
-```
-
-The configuration for the example design is contained in `example.yml` and the entry script with hooks is contained in `example-vlsi`. You may go through Hammer's readme to learn about the supported configuration options and how to write hooks.
-
-In order to install the process, download (and optionally extract) the ASAP7 PDK tarball. Then, edit the key `vlsi.technology.asap7.tarball_dir` if you want Hammer to extract for you or `vlsi.technology.asap7.install_dir` if you have already extracted it.
-
-To synthesize the just the SHA-3 accelerator with the hard macro we have to change the physical top module (this step is not necessary if you are pushing the entire Rocket-chip through the VLSI flow):
-```shell
-export TOP=Sha3AccelwBB
-rm build/inputs.yml
-```
-
-Then, to run synthesis:
-```shell
-make syn
-```
-
-The outputs are written to a log file with a timestamp and the post-synthesis results are in `build/syn-rundir`.
-
-Raw QoR data is available at `build/syn-rundir/reports`, and work is planned to extract this information in a more programmatic manner.
-
-To run place and route:
-```shell
-make par
-```
-
-If successful, the resulting chip can be opened via `./build/par-rundir/generated-scripts/open_chip`.
-
-To run DRC and view violations:
-```shell
-make drc
-./build/drc-rundir/generated-scripts/view-drc
-```
-
-To run LVS and view violations:
-```shell
-make lvs
-./build/lvs-rundir/generated-scripts/view-lvs
-```

vlsi/example.yml

@@ -43,8 +43,6 @@ par.generate_power_straps_options:
       - M8
       - M9
     track_width: 5
-    track_width_M8: 6
-    track_width_M9: 6
     track_spacing: 0
     track_start: 10
     power_utilization: 0.05
@@ -60,10 +58,10 @@ vlsi.inputs.placement_constraints:
     width: 300
     height: 300
     margins:
-      left: 10
-      right: 10
-      top: 10
-      bottom: 10
+      left: 0
+      right: 0
+      top: 0
+      bottom: 1.08 #must be at least this number
   - path: "Sha3AccelwBB/dco"
     type: "hardmacro"
     x: 100