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Upgrade verilator to support permissive args in the same way as vcs

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It previously only supported them as the last argument.
Supporting them in this case would have removed some of
the DRY code that is able to handle both simulators.
This commit is contained in:
Colin Schmidt
2020-05-24 09:29:22 -07:00
parent c2c9bc83de
commit 29664cdf6a
2 changed files with 29 additions and 16 deletions
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4
sims/verilator/Makefile
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@@ -28,8 +28,8 @@ sim_prefix = simulator
sim = $(sim_dir)/$(sim_prefix)-$(MODEL_PACKAGE)-$(CONFIG)
sim_debug = $(sim_dir)/$(sim_prefix)-$(MODEL_PACKAGE)-$(CONFIG)-debug
PERMISSIVE_ON=
PERMISSIVE_OFF=
PERMISSIVE_ON=+permissive
PERMISSIVE_OFF=+permissive-off
WAVEFORM_FLAG=-v$(sim_out_name).vcd