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@@ -51,22 +51,22 @@ vlsi.inputs.placement_constraints:
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y: 1900
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orientation: r0
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- path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_5_0"
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type: hardmacro
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x: 1000
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x: 1000
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y: 1300
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orientation: r0
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- path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_6_0"
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type: hardmacro
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x: 1000
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x: 1000
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y: 700
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orientation: r0
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- path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_7_0"
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type: hardmacro
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x: 1000
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x: 1000
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y: 100
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orientation: r0
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@@ -87,4 +87,4 @@ vlsi.inputs.placement_constraints:
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type: hardmacro
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x: 3450
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y: 1300
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orientation: r0
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orientation: r0
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