Run pre-commit on all files

2022-12-21 15:59:46 -08:00
parent d63c3cb72e
commit 292cc753ce
59 changed files with 76 additions and 115 deletions
--- a/vlsi/example-asap7.yml
+++ b/vlsi/example-asap7.yml
@@ -20,7 +20,7 @@ vlsi.inputs.clocks: [
  {name: "clock_clock", period: "1ns", uncertainty: "0.1ns"}
 ]

-# Generate Make include to aid in flow 
+# Generate Make include to aid in flow
 vlsi.core.build_system: make

 # Placement Constraints
@@ -52,7 +52,7 @@ vlsi.inputs.placement_constraints:
    top_layer: "M4"
  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_0_2"
    type: hardmacro
-    x: 675 
+    x: 675
    y: 25
    orientation: "r0"
    top_layer: "M4"