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abejgonzalez
2022-12-21 15:59:46 -08:00
parent d63c3cb72e
commit 292cc753ce
59 changed files with 76 additions and 115 deletions
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generators/firechip/src/main/scala/TargetConfigs.scala
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@@ -109,7 +109,7 @@ class WithFireSimHighPerfClocking extends Config(
// Tweaks that are generally applied to all firesim configs setting a single clock domain at 1000 MHz
class WithFireSimConfigTweaks extends Config(
// 1 GHz matches the FASED default (DRAM modeli realistically configured for that frequency)
// Using some other frequency will require runnings the FASED runtime configuration generator
// Using some other frequency will require runnings the FASED runtime configuration generator
// to generate faithful DDR3 timing values.
new chipyard.config.WithSystemBusFrequency(1000.0) ++
new chipyard.config.WithSystemBusFrequencyAsDefault ++ // All unspecified clock frequencies, notably the implicit clock, will use the sbus freq (1000 MHz)