Run pre-commit on all files

generators/chipyard/src/main/resources/vsrc/GCDMMIOBlackBox.v

@@ -17,7 +17,7 @@ module GCDMMIOBlackBox
 
    localparam S_IDLE = 2'b00, S_RUN = 2'b01, S_DONE = 2'b10;
 
-   reg [1:0]               state;   
+   reg [1:0]               state;
    reg [WIDTH-1:0]         tmp;
 
    assign input_ready = state == S_IDLE;
@@ -34,12 +34,12 @@ module GCDMMIOBlackBox
       else if (state == S_DONE && output_ready)
         state <= S_IDLE;
    end
-   
+
    always @(posedge clock) begin
       if (state == S_IDLE && input_valid) begin
          gcd <= x;
          tmp <= y;
-      end else if (state == S_RUN) begin  
+      end else if (state == S_RUN) begin
          if (gcd > tmp)
            gcd <= gcd - tmp;
          else

generators/chipyard/src/main/scala/ChipTop.scala

@@ -33,4 +33,3 @@ class ChipTop(implicit p: Parameters) extends LazyModule with BindingScope
   // anyways, they probably need to be explicitly clocked.
   lazy val module: LazyModuleImpLike = new LazyRawModuleImp(this) {  }
 }
-

generators/chipyard/src/main/scala/Subsystem.scala

@@ -83,4 +83,3 @@ class ChipyardSubsystemModuleImp[+L <: ChipyardSubsystem](_outer: L) extends Bas
   // This is included in the `dromajo_params.h` header file
   DromajoHelper.addArtefacts(InSubsystem)
 }
-

generators/chipyard/src/main/scala/TestHarness.scala

@@ -108,4 +108,3 @@ class TestHarness(implicit val p: Parameters) extends Module with HasHarnessSign
   implicitHarnessClockBundle.reset := reset
   p(HarnessClockInstantiatorKey).instantiateHarnessDividerPLL(implicitHarnessClockBundle)
 }
-

generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala

@@ -86,4 +86,3 @@ trait HasChipyardPRCI { this: BaseSubsystem with InstantiatesTiles =>
     := tileResetSetter
     := allClockGroupsNode)
 }
-

generators/chipyard/src/main/scala/clocking/TileClockGater.scala

@@ -14,9 +14,9 @@ import freechips.rocketchip.devices.tilelink._
 import freechips.rocketchip.regmapper._
 import freechips.rocketchip.subsystem._
 
-/** This node adds clock gating control registers. 
+/** This node adds clock gating control registers.
   * If deploying on a platform which does not support clock gating, deasserting the enable
-  * flag will generate the registers, preserving the same memory map and behavior, but will not 
+  * flag will generate the registers, preserving the same memory map and behavior, but will not
   * generate any gaters
   */
 class TileClockGater(address: BigInt, beatBytes: Int, enable: Boolean)(implicit p: Parameters, valName: ValName) extends LazyModule

generators/chipyard/src/main/scala/config/IbexConfigs.scala

@@ -12,4 +12,4 @@ import freechips.rocketchip.config.{Config}
 
 class IbexConfig extends Config(
   new ibex.WithNIbexCores(1) ++
-  new chipyard.config.AbstractConfig)
+  new chipyard.config.AbstractConfig)

generators/chipyard/src/main/scala/config/RocketSha3Configs.scala

@@ -20,4 +20,3 @@ class Sha3RocketPrintfConfig extends Config(
   new sha3.WithSha3Accel ++                                // add SHA3 rocc accelerator
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++
   new chipyard.config.AbstractConfig)
-

generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala

@@ -75,4 +75,3 @@ class WithSerialTLBackingMemory extends Config((site, here, up) => {
 class WithExtMemIdBits(n: Int) extends Config((site, here, up) => {
     case ExtMem => up(ExtMem, site).map(x => x.copy(master = x.master.copy(idBits = n)))
 })
-

generators/chipyard/src/main/scala/config/fragments/TileFragments.scala

@@ -68,4 +68,3 @@ class WithRocketDCacheScratchpad extends Config((site, here, up) => {
     ))
   }
 })
-

generators/chipyard/src/main/scala/config/fragments/TracegenFragments.scala

@@ -11,4 +11,3 @@ class TraceGenTop(implicit p: Parameters) extends TraceGenSystem
 class WithTracegenSystem extends Config((site, here, up) => {
   case BuildSystem => (p: Parameters) => new TraceGenTop()(p)
 })
-

generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala

@@ -145,4 +145,3 @@ trait CanHavePeripheryStreamingPassthrough { this: BaseSubsystem =>
 class WithStreamingPassthrough extends Config((site, here, up) => {
   case StreamingPassthroughKey => Some(StreamingPassthroughParams(depth = 8))
 })
-

generators/chipyard/src/main/scala/stage/ChipyardAnnotations.scala

@@ -23,4 +23,3 @@ private[stage] object UnderscoreDelimitedConfigsAnnotation extends HasShellOptio
     )
   )
 }
-

generators/chipyard/src/test/scala/clocking/SimplePllConfigurationSpec.scala

@@ -14,7 +14,7 @@ class SimplePllConfigurationSpec extends org.scalatest.flatspec.AnyFlatSpec {
 
     def trySuccessfulConf(requestedFreqs: Seq[Double], expected: Double): Unit = {
       val freqStr = requestedFreqs.mkString(", ")
-      it should s"select a reference of ${expected} MHz for ${freqStr} MHz" in { 
+      it should s"select a reference of ${expected} MHz for ${freqStr} MHz" in {
         val conf = genConf(requestedFreqs)
         conf.emitSummaries
         assert(expected == conf.referenceFreqMHz)

generators/firechip/src/main/scala/TargetConfigs.scala

@@ -109,7 +109,7 @@ class WithFireSimHighPerfClocking extends Config(
 // Tweaks that are generally applied to all firesim configs setting a single clock domain at 1000 MHz
 class WithFireSimConfigTweaks extends Config(
   // 1 GHz matches the FASED default (DRAM modeli realistically configured for that frequency)
-  // Using some other frequency will require runnings the FASED runtime configuration generator 
+  // Using some other frequency will require runnings the FASED runtime configuration generator
   // to generate faithful DDR3 timing values.
   new chipyard.config.WithSystemBusFrequency(1000.0) ++
   new chipyard.config.WithSystemBusFrequencyAsDefault ++ // All unspecified clock frequencies, notably the implicit clock, will use the sbus freq (1000 MHz)