Run pre-commit on all files

2022-12-21 15:59:46 -08:00
parent d63c3cb72e
commit 292cc753ce
59 changed files with 76 additions and 115 deletions
--- a/fpga/src/main/scala/vc707/TestHarness.scala
+++ b/fpga/src/main/scala/vc707/TestHarness.scala
@@ -91,7 +91,7 @@ class VC707FPGATestHarness(override implicit val p: Parameters) extends VC707She
 }

 class VC707FPGATestHarnessImp(_outer: VC707FPGATestHarness) extends LazyRawModuleImp(_outer) with HasHarnessSignalReferences {
-  
+
  val vc707Outer = _outer

  val reset = IO(Input(Bool()))