Run pre-commit on all files

fpga/src/main/scala/arty/TestHarness.scala

@@ -38,4 +38,3 @@ class ArtyFPGATestHarness(override implicit val p: Parameters) extends ArtyShell
     ApplyHarnessBinders(this, d.lazySystem, d.portMap)
   }
 }
-

fpga/src/main/scala/vc707/TestHarness.scala

@@ -91,7 +91,7 @@ class VC707FPGATestHarness(override implicit val p: Parameters) extends VC707She
 }
 
 class VC707FPGATestHarnessImp(_outer: VC707FPGATestHarness) extends LazyRawModuleImp(_outer) with HasHarnessSignalReferences {
-  
+
   val vc707Outer = _outer
 
   val reset = IO(Input(Bool()))

fpga/src/main/scala/vcu118/CustomOverlays.scala

@@ -107,4 +107,3 @@ class DDR2VCU118ShellPlacer(shell: VCU118FPGATestHarness, val shellInput: DDRShe
   extends DDRShellPlacer[VCU118FPGATestHarness] {
   def place(designInput: DDRDesignInput) = new DDR2VCU118PlacedOverlay(shell, valName.name, designInput, shellInput)
 }
-