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docs/TileLink-Diplomacy-Reference/Diplomacy-Connectors.rst

@@ -9,7 +9,7 @@ library provides four operators that can be used to form edges between nodes.
 
 This is the basic connection operator. It is the same syntax as the Chisel
 uni-directional connector, but it is not equivalent. This operator connects
-Diplomacy nodes, not Chisel bundles. 
+Diplomacy nodes, not Chisel bundles.
 
 The basic connection operator always creates a single edge between the two
 nodes.

docs/TileLink-Diplomacy-Reference/Register-Router.rst

@@ -2,15 +2,15 @@ Register Router
 ===============
 
 Memory-mapped devices generally follow a common pattern. They expose a set
-of registers to the CPUs. By writing to a register, the CPU can change the 
+of registers to the CPUs. By writing to a register, the CPU can change the
 device's settings or send a command. By reading from a register, the CPU can
 query the device's state or retrieve results.
 
-While designers can manually instantiate a manager node and write the logic 
+While designers can manually instantiate a manager node and write the logic
 for exposing registers themselves, it's much easier to use RocketChip's
 ``regmap`` interface, which can generate most of the glue logic.
 
-For TileLink devices, you can use the ``regmap`` interface by extending 
+For TileLink devices, you can use the ``regmap`` interface by extending
 the ``TLRegisterRouter`` class, as shown in :ref:`mmio-accelerators`,
 or you can create a regular LazyModule and instantiate a ``TLRegisterNode``.
 This section will focus on the second method.

docs/TileLink-Diplomacy-Reference/Widgets.rst

@@ -465,6 +465,3 @@ if you want multi-beat reads/writes.
 AXI4RAM only supports AXI4-Lite operations, so multi-beat reads/writes and
 reads/writes smaller than full-width are not supported. Use an ``AXI4Fragmenter``
 if you want to use the full AXI4 protocol.
-
-
-