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Update section header on Verilog support in chipyard tools

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Albert Magyar
2019-09-26 09:50:41 -07:00
parent 216ae3ee54
commit 28664ea8df
1 changed files with 2 additions and 2 deletions
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docs/Customization/Incorporating-Verilog-Blocks.rst
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@@ -158,8 +158,8 @@ write.
:start-after: DOC include start: GCD test :start-after: DOC include start: GCD test
:end-before: DOC include end: GCD test :end-before: DOC include end: GCD test
Support for Verilog in Downstream Berkeley Tools Support for Verilog Within Chipyard Tool Flows
------------------------------------------------ ----------------------------------------------
There are important differences in how Verilog blackboxes are treated There are important differences in how Verilog blackboxes are treated
by downstream tools. Since they remain blackboxes in FIRRTL, their by downstream tools. Since they remain blackboxes in FIRRTL, their