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Remove Dromajo + documentation

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This commit is contained in:
abejgonzalez
2023-09-06 13:30:24 -07:00
parent 12248a221c
commit 284f276fbb
16 changed files with 1570 additions and 1461 deletions
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5
generators/chipyard/src/main/scala/Subsystem.scala
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@@ -24,7 +24,7 @@ import freechips.rocketchip.amba.axi4._
import boom.common.{BoomTile}
import testchipip.{DromajoHelper, CanHavePeripheryTLSerial, SerialTLKey}
import testchipip.{CanHavePeripheryTLSerial, SerialTLKey}
trait CanHaveHTIF { this: BaseSubsystem =>
// Advertise HTIF if system can communicate with fesvr
@@ -124,7 +124,4 @@ class ChipyardSubsystem(implicit p: Parameters) extends BaseSubsystem
class ChipyardSubsystemModuleImp[+L <: ChipyardSubsystem](_outer: L) extends BaseSubsystemModuleImp(_outer)
with HasTilesModuleImp
{
// Generate C header with relevant information for Dromajo
// This is included in the `dromajo_params.h` header file
DromajoHelper.addArtefacts(InSubsystem)
}

7
generators/chipyard/src/main/scala/config/BoomConfigs.scala
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@@ -41,13 +41,6 @@ class LoopbackNICLargeBoomConfig extends Config(
new chipyard.config.WithSystemBusWidth(128) ++
new chipyard.config.AbstractConfig)
class DromajoBoomConfig extends Config(
new chipyard.harness.WithSimDromajoBridge ++ // attach Dromajo
new chipyard.config.WithTraceIO ++ // enable the traceio
new boom.common.WithNSmallBooms(1) ++
new chipyard.config.WithSystemBusWidth(128) ++
new chipyard.config.AbstractConfig)
class MediumBoomCosimConfig extends Config(
new chipyard.harness.WithCospike ++ // attach spike-cosim
new chipyard.config.WithTraceIO ++ // enable the traceio

6
generators/chipyard/src/main/scala/harness/HarnessBinders.scala
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@@ -352,12 +352,6 @@ class WithTraceGenSuccess extends OverrideHarnessBinder({
}
})
class WithSimDromajoBridge extends ComposeHarnessBinder({
(system: CanHaveTraceIOModuleImp, th: HasHarnessInstantiators, ports: Seq[TraceOutputTop]) => {
ports.map { p => p.traces.map(tileTrace => SimDromajoBridge(tileTrace)(system.p)) }
}
})
class WithCospike extends ComposeHarnessBinder({
(system: CanHaveTraceIOModuleImp, th: HasHarnessInstantiators, ports: Seq[TraceOutputTop]) => {
implicit val p = chipyard.iobinders.GetSystemParameters(system)