update to tilelink2
This commit is contained in:
Howard Mao
@@ -2,22 +2,24 @@ package pwm
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import chisel3._
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import chisel3.util._
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import cde.{Parameters, Field}
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import config.{Parameters, Field}
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import uncore.tilelink._
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import uncore.tilelink2._
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import junctions._
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import diplomacy._
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import rocketchip._
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import _root_.util.UIntIsOneOf
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class PWMBase extends Module {
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class PWMBase(w: Int) extends Module {
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val io = IO(new Bundle {
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val pwmout = Output(Bool())
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val period = Input(UInt(64.W))
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val duty = Input(UInt(64.W))
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val period = Input(UInt(w.W))
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val duty = Input(UInt(w.W))
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val enable = Input(Bool())
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})
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// The counter should count up until period is reached
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val counter = Reg(UInt(64.W))
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val counter = Reg(UInt(w.W))
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when (counter >= (io.period - 1.U)) {
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counter := 0.U
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@@ -30,62 +32,70 @@ class PWMBase extends Module {
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io.pwmout := io.enable && (counter < io.duty)
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}
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class PWMTL(implicit p: Parameters) extends Module {
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class PWMTL(address: AddressSet, beatBytes: Int)(implicit p: Parameters) extends LazyModule {
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val node = TLManagerNode(Seq(TLManagerPortParameters(
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Seq(TLManagerParameters(
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address = List(address),
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regionType = RegionType.PUT_EFFECTS,
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executable = false,
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supportsGet = TransferSizes(1, beatBytes),
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supportsPutFull = TransferSizes(1, beatBytes),
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fifoId = Some(0))), // requests are handled in order
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beatBytes = beatBytes,
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minLatency = 1)))
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lazy val module = new PWMTLModule(this, beatBytes)
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}
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class PWMTLModule(outer: PWMTL, beatBytes: Int) extends LazyModuleImp(outer) {
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val io = IO(new Bundle {
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val pwmout = Output(Bool())
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val tl = Flipped(new ClientUncachedTileLinkIO())
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val tl = outer.node.bundleIn
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})
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val w = beatBytes * 8
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// How many clock cycles in a PWM cycle?
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val period = Reg(UInt(64.W))
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val period = Reg(UInt(w.W))
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// For how many cycles should the clock be high?
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val duty = Reg(UInt(64.W))
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val duty = Reg(UInt(w.W))
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// Is the PWM even running at all?
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val enable = Reg(init = false.B)
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val base = Module(new PWMBase)
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val base = Module(new PWMBase(w))
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io.pwmout := base.io.pwmout
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base.io.period := period
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base.io.duty := duty
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base.io.enable := enable
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val tl = io.tl.head
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tl.b.valid := false.B
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tl.c.ready := false.B
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tl.e.ready := false.B
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// One entry queue to hold the acquire message
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val acq = Queue(io.tl.acquire, 1)
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val acq = Queue(tl.a, 1)
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// We assume that the TileLink interface is 64 bits wide
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require(io.tl.tlDataBits == 64)
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// We have 3 32-bit registers
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val index = acq.bits.address(3, 2)
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// Then addr_block and addr_beat together form the word address
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val full_addr = Cat(acq.bits.addr_block, acq.bits.addr_beat)
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// Since we have 3 registers, we only need the lower two bits to distinguish them
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val index = full_addr(1, 0)
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// Make sure the acquires we get are only the types we expect
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assert(!acq.valid ||
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acq.bits.isBuiltInType(Acquire.getType) ||
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acq.bits.isBuiltInType(Acquire.putType))
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// Make sure write masks are full
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assert(!acq.valid || !acq.bits.hasData() ||
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acq.bits.wmask() === Acquire.fullWriteMask)
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val edge = outer.node.edgesIn(0)
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val hasData = edge.hasData(acq.bits)
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// Base the grant on the stored acquire
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io.tl.grant.valid := acq.valid
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acq.ready := io.tl.grant.ready
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io.tl.grant.bits := Grant(
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is_builtin_type = true.B,
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g_type = acq.bits.getBuiltInGrantType(),
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client_xact_id = acq.bits.client_xact_id,
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manager_xact_id = 0.U,
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addr_beat = acq.bits.addr_beat,
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// For gets, map the index to the three registers
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data = MuxLookup(index, 0.U, Seq(
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tl.d.valid := acq.valid
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acq.ready := tl.d.ready
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tl.d.bits := edge.AccessAck(acq.bits, 0.U)
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tl.d.bits.opcode := Mux(hasData, TLMessages.AccessAck, TLMessages.AccessAckData)
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tl.d.bits.data := MuxLookup(index, 0.U,
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Seq(
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0.U -> period,
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1.U -> duty,
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2.U -> enable)))
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2.U -> enable))
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tl.d.bits.error := index > 2.U
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// If this is a put, update the registers according to the index
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when (acq.fire() && acq.bits.hasData()) {
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when (acq.fire() && acq.bits.opcode === TLMessages.PutFullData) {
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switch (index) {
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is (0.U) { period := acq.bits.data }
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is (1.U) { duty := acq.bits.data }
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@@ -94,79 +104,24 @@ class PWMTL(implicit p: Parameters) extends Module {
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}
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}
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class PWMAXI(implicit p: Parameters) extends Module {
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val io = IO(new Bundle {
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val pwmout = Output(Bool())
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val axi = Flipped(new NastiIO())
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})
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trait PeripheryPWM extends LazyModule with HasPeripheryParameters {
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implicit val p: Parameters
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val peripheryBus: TLXbar
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// How many clock cycles in a PWM cycle?
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val period = Reg(UInt(64.W))
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// For how many cycles should the clock be high?
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val duty = Reg(UInt(64.W))
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// Is the PWM even running at all?
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val enable = Reg(init = false.B)
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val base = Module(new PWMBase)
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io.pwmout := base.io.pwmout
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base.io.period := period
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base.io.duty := duty
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base.io.enable := enable
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val ar = Queue(io.axi.ar, 1)
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val aw = Queue(io.axi.aw, 1)
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val w = Queue(io.axi.w, 1)
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// Start from 3rd bit since 64-bit words
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// Only need 2 bits, since 3 registers
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val read_index = ar.bits.addr(4, 3)
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val write_index = aw.bits.addr(4, 3)
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io.axi.r.valid := ar.valid
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ar.ready := io.axi.r.ready
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io.axi.r.bits := NastiReadDataChannel(
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id = ar.bits.id,
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data = MuxLookup(read_index, 0.U, Seq(
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0.U -> period,
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1.U -> duty,
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2.U -> enable)))
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io.axi.b.valid := aw.valid && w.valid
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aw.ready := io.axi.b.ready && w.valid
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w.ready := io.axi.b.ready && aw.valid
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io.axi.b.bits := NastiWriteResponseChannel(id = aw.bits.id)
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when (io.axi.b.fire()) {
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switch (write_index) {
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is (0.U) { period := w.bits.data }
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is (1.U) { duty := w.bits.data }
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is (2.U) { enable := w.bits.data(0) }
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}
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}
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require(io.axi.w.bits.nastiXDataBits == 64)
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assert(!io.axi.ar.valid || (io.axi.ar.bits.len === 0.U && io.axi.ar.bits.size === 3.U))
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assert(!io.axi.aw.valid || (io.axi.aw.bits.len === 0.U && io.axi.aw.bits.size === 3.U))
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assert(!io.axi.w.valid || PopCount(io.axi.w.bits.strb) === 8.U)
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}
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trait PeripheryPWM extends LazyModule {
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val pDevices: ResourceManager[AddrMapEntry]
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pDevices.add(AddrMapEntry("pwm", MemSize(4096, MemAttr(AddrMapProt.RW))))
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private val address = AddressSet(0x2000, 0xfff)
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val pwm = LazyModule(new PWMTL(address, peripheryBusConfig.beatBytes)(p))
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pwm.node := TLFragmenter(
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peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node)
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}
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trait PeripheryPWMBundle {
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val pwmout = Output(Bool())
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}
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case object BuildPWM extends Field[(ClientUncachedTileLinkIO, Parameters) => Bool]
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trait PeripheryPWMModule extends HasPeripheryParameters {
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implicit val p: Parameters
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val pBus: TileLinkRecursiveInterconnect
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val io: PeripheryPWMBundle
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val outer: PeripheryPWM
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io.pwmout := p(BuildPWM)(pBus.port("pwm"), outerMMIOParams)
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io.pwmout := outer.pwm.module.io.pwmout
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}
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