update to tilelink2

src/main/scala/example/Configs.scala

@@ -1,7 +1,7 @@
 package example
 
-import cde.{Parameters, Config, CDEMatchError}
+import config.{Parameters, Config}
 import testchipip.WithSerialAdapter
 
 class DefaultExampleConfig extends Config(
-  new WithSerialAdapter ++ new rocketchip.BaseConfig)
+  new WithSerialAdapter ++ new rocketchip.DefaultConfig)

src/main/scala/example/TestHarness.scala

@@ -5,24 +5,26 @@ import diplomacy.LazyModule
 import rocketchip._
 import testchipip._
 import chisel3._
-import cde.Parameters
+import config.Parameters
 
 class TestHarness(implicit val p: Parameters) extends Module {
   val io = IO(new Bundle {
     val success = Output(Bool())
   })
 
-  def buildTop(p: Parameters): ExampleTop = LazyModule(new ExampleTop(p))
+  def buildTop(p: Parameters): ExampleTop = LazyModule(new ExampleTop()(p))
 
-  val dut = buildTop(p).module
+  val dut = Module(buildTop(p).module)
   val ser = Module(new SimSerialWrapper(p(SerialInterfaceWidth)))
 
-  val nMemChannels = dut.io.mem_axi.size
-  for (axi <- dut.io.mem_axi) {
-    val mem = Module(new SimAXIMem(BigInt(p(ExtMemSize) / nMemChannels)))
-    mem.io.axi <> axi
+  dut.io.debug.map { dbg =>
+    dbg.req.valid := false.B
+    dbg.resp.ready := false.B
   }
 
+  val nMemChannels = p(coreplex.BankedL2Config).nMemoryChannels
+  val mem = Module(LazyModule(new SimAXIMem(nMemChannels)).module)
+  mem.io.axi4 <> dut.io.mem_axi4
   ser.io.serial <> dut.io.serial
   io.success := ser.io.exit
 }

src/main/scala/example/Top.scala

@@ -1,23 +1,39 @@
 package example
 
 import chisel3._
-import cde.Parameters
+import config.Parameters
 import testchipip._
 import rocketchip._
 
-class ExampleTop(q: Parameters) extends BaseTop(q)
-    with PeripheryBootROM with PeripheryCoreplexLocalInterrupter
-    with PeripherySerial with PeripheryMasterMem {
-  override lazy val module = Module(
-    new ExampleTopModule(p, this, new ExampleTopBundle(p)))
+class ExampleTop(implicit p: Parameters) extends BaseTop()(p)
+    with PeripheryMasterAXI4Mem
+    with PeripheryBootROM
+    with PeripheryZero
+    with PeripheryCounter
+    with PeripheryDebug
+    with HardwiredResetVector
+    with RocketPlexMaster
+    with PeripherySerial {
+  override lazy val module = new ExampleTopModule(this, () => new ExampleTopBundle(this))
 }
 
-class ExampleTopBundle(p: Parameters) extends BaseTopBundle(p)
-  with PeripheryBootROMBundle with PeripheryCoreplexLocalInterrupterBundle
-  with PeripheryMasterMemBundle with PeripherySerialBundle
+class ExampleTopBundle[+L <: ExampleTop](l: L) extends BaseTopBundle(l)
+    with PeripheryMasterAXI4MemBundle
+    with PeripheryBootROMBundle
+    with PeripheryZeroBundle
+    with PeripheryCounterBundle
+    with PeripheryDebugBundle
+    with HardwiredResetVectorBundle
+    with RocketPlexMasterBundle
+    with PeripherySerialBundle
 
-class ExampleTopModule[+L <: ExampleTop, +B <: ExampleTopBundle](p: Parameters, l: L, b: => B)
-  extends BaseTopModule(p, l, b)
-  with PeripheryBootROMModule with PeripheryCoreplexLocalInterrupterModule
-  with PeripheryMasterMemModule with PeripherySerialModule
-  with HardwiredResetVector with DirectConnection with NoDebug
+class ExampleTopModule[+L <: ExampleTop, +B <: ExampleTopBundle[L]](l: L, b: () => B)
+  extends BaseTopModule(l, b)
+    with PeripheryMasterAXI4MemModule
+    with PeripheryBootROMModule
+    with PeripheryZeroModule
+    with PeripheryCounterModule
+    with PeripheryDebugModule
+    with HardwiredResetVectorModule
+    with RocketPlexMasterModule
+    with PeripherySerialModule