diff --git a/generators/firechip/src/main/scala/SimConfigs.scala b/generators/firechip/src/main/scala/SimConfigs.scala
index 1118fe07..937c2877 100644
--- a/generators/firechip/src/main/scala/SimConfigs.scala
+++ b/generators/firechip/src/main/scala/SimConfigs.scala
@@ -52,3 +52,7 @@ class FireSimDDR3FRFCFSLLC4MB3ClockDivConfig extends Config(
   new FRFCFS16GBQuadRankLLC4MB3Div ++
   new FireSimConfig)
 
+class Midas2Config extends Config(
+  new WithMultiCycleRamModels ++
+  new FireSimConfig)
+
diff --git a/generators/firechip/src/main/scala/TargetMixins.scala b/generators/firechip/src/main/scala/TargetMixins.scala
index 7b4d5d4f..535e354a 100644
--- a/generators/firechip/src/main/scala/TargetMixins.scala
+++ b/generators/firechip/src/main/scala/TargetMixins.scala
@@ -1,6 +1,7 @@
 package firesim.firesim
 
 import chisel3._
+import chisel3.experimental.annotate
 import freechips.rocketchip.config.{Field, Parameters}
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.tilelink._
@@ -12,7 +13,31 @@ import freechips.rocketchip.rocket.TracedInstruction
 import firesim.endpoints.{TraceOutputTop, DeclockedTracedInstruction}
 
 import midas.models.AXI4BundleWithEdge
-import midas.targetutils.ExcludeInstanceAsserts
+import midas.targetutils.{ExcludeInstanceAsserts, MemModelAnnotation}
+
+/** Ties together Subsystem buses in the same fashion done in the example top of Rocket Chip */
+trait HasDefaultBusConfiguration {
+  this: BaseSubsystem =>
+  // The sbus masters the cbus; here we convert TL-UH -> TL-UL
+  sbus.crossToBus(cbus, NoCrossing)
+
+  // The cbus masters the pbus; which might be clocked slower
+  cbus.crossToBus(pbus, SynchronousCrossing())
+
+  // The fbus masters the sbus; both are TL-UH or TL-C
+  FlipRendering { implicit p =>
+    sbus.crossFromBus(fbus, SynchronousCrossing())
+  }
+
+  // The sbus masters the mbus; here we convert TL-C -> TL-UH
+  private val BankedL2Params(nBanks, coherenceManager) = p(BankedL2Key)
+  private val (in, out, halt) = coherenceManager(this)
+  if (nBanks != 0) {
+    sbus.coupleTo("coherence_manager") { in :*= _ }
+    mbus.coupleFrom("coherence_manager") { _ :=* BankBinder(mbus.blockBytes * (nBanks-1)) :*= out }
+  }
+}
+
 
 /** Copied from RC and modified to change the IO type of the Imp to include the Diplomatic edges
   *  associated with each port. This drives FASED functional model sizing
@@ -104,3 +129,26 @@ trait ExcludeInvalidBoomAssertions extends LazyModuleImp {
   ExcludeInstanceAsserts(("NonBlockingDCache", "dtlb"))
 }
 
+trait CanHaveBoomMultiCycleRegfileImp {
+  val outer: boom.system.BoomRocketSubsystem
+  val cores = outer.boomTiles.map(tile => tile.module.core)
+  cores.foreach({ core =>
+    core.iregfile match {
+      case irf: boom.exu.RegisterFileSynthesizable => annotate(MemModelAnnotation(irf.regfile))
+      case _ => Nil
+    }
+
+     if (core.fp_pipeline != null) core.fp_pipeline.fregfile match {
+      case irf: boom.exu.RegisterFileSynthesizable => annotate(MemModelAnnotation(irf.regfile))
+      case _ => Nil
+    }
+
+   })
+}
+trait CanHaveRocketMultiCycleRegfileImp {
+  val outer: RocketSubsystem
+  outer.rocketTiles.foreach({ tile =>
+    annotate(MemModelAnnotation(tile.module.core.rocketImpl.rf.rf))
+    tile.module.fpuOpt.foreach(fpu => annotate(MemModelAnnotation(fpu.fpuImpl.regfile)))
+  })
+}
diff --git a/generators/firechip/src/main/scala/Targets.scala b/generators/firechip/src/main/scala/Targets.scala
index 7f8bb830..34477509 100644
--- a/generators/firechip/src/main/scala/Targets.scala
+++ b/generators/firechip/src/main/scala/Targets.scala
@@ -31,7 +31,7 @@ import java.io.File
 *******************************************************************************/
 
 class FireSim(implicit p: Parameters) extends RocketSubsystem
-    with HasHierarchicalBusTopology
+    with HasDefaultBusConfiguration
     with CanHaveFASEDOptimizedMasterAXI4MemPort
     with HasPeripheryBootROM
     with HasNoDebug
@@ -54,10 +54,11 @@ class FireSimModuleImp[+L <: FireSim](l: L) extends RocketSubsystemModuleImp(l)
     with HasPeripheryIceNICModuleImpValidOnly
     with HasPeripheryBlockDeviceModuleImp
     with HasTraceIOImp
+    with CanHaveRocketMultiCycleRegfileImp
 
 
 class FireSimNoNIC(implicit p: Parameters) extends RocketSubsystem
-    with HasHierarchicalBusTopology
+    with HasDefaultBusConfiguration
     with CanHaveFASEDOptimizedMasterAXI4MemPort
     with HasPeripheryBootROM
     with HasNoDebug
@@ -78,10 +79,11 @@ class FireSimNoNICModuleImp[+L <: FireSimNoNIC](l: L) extends RocketSubsystemMod
     with HasPeripheryUARTModuleImp
     with HasPeripheryBlockDeviceModuleImp
     with HasTraceIOImp
+    with CanHaveRocketMultiCycleRegfileImp
 
 
 class FireBoom(implicit p: Parameters) extends BoomRocketSubsystem
-    with HasHierarchicalBusTopology
+    with HasDefaultBusConfiguration
     with CanHaveFASEDOptimizedMasterAXI4MemPort
     with HasPeripheryBootROM
     with HasNoDebug
@@ -105,9 +107,10 @@ class FireBoomModuleImp[+L <: FireBoom](l: L) extends BoomRocketSubsystemModuleI
     with HasPeripheryBlockDeviceModuleImp
     with HasTraceIOImp
     with ExcludeInvalidBoomAssertions
+    with CanHaveBoomMultiCycleRegfileImp
 
 class FireBoomNoNIC(implicit p: Parameters) extends BoomRocketSubsystem
-    with HasHierarchicalBusTopology
+    with HasDefaultBusConfiguration
     with CanHaveFASEDOptimizedMasterAXI4MemPort
     with HasPeripheryBootROM
     with HasNoDebug
@@ -129,6 +132,7 @@ class FireBoomNoNICModuleImp[+L <: FireBoomNoNIC](l: L) extends BoomRocketSubsys
     with HasPeripheryBlockDeviceModuleImp
     with HasTraceIOImp
     with ExcludeInvalidBoomAssertions
+    with CanHaveBoomMultiCycleRegfileImp
 
 case object NumNodes extends Field[Int]
 
diff --git a/generators/firechip/src/test/scala/ScalaTestSuite.scala b/generators/firechip/src/test/scala/ScalaTestSuite.scala
index 54848ac8..44c4bff0 100644
--- a/generators/firechip/src/test/scala/ScalaTestSuite.scala
+++ b/generators/firechip/src/test/scala/ScalaTestSuite.scala
@@ -109,9 +109,9 @@ abstract class FireSimTestSuite(
         val lines = Source.fromFile(file).getLines.toList
         lines.filter(_.startsWith("TRACEPORT")).drop(dropLines)
       }
-      val resetLength = 50
+      val resetLength = 51
       val verilatedOutput  = getLines(new File(outDir,  s"/${verilatedLog}"))
-      val synthPrintOutput = getLines(new File(genDir, s"/TRACEFILE"), resetLength + 1)
+      val synthPrintOutput = getLines(new File(genDir, s"/TRACEFILE"), resetLength)
       assert(verilatedOutput.size == synthPrintOutput.size, "Outputs differ in length")
       assert(verilatedOutput.nonEmpty)
       for ( (vPrint, sPrint) <- verilatedOutput.zip(synthPrintOutput) ) {
@@ -131,8 +131,9 @@ abstract class FireSimTestSuite(
 }
 
 class RocketF1Tests extends FireSimTestSuite("FireSimNoNIC", "FireSimRocketChipConfig", "FireSimConfig")
-class RocketF1ClockDivTests extends FireSimTestSuite("FireSimNoNIC", "FireSimRocketChipConfig", "FireSimClockDivConfig")
 class BoomF1Tests extends FireSimTestSuite("FireBoomNoNIC", "FireSimBoomConfig", "FireSimConfig")
 class RocketNICF1Tests extends FireSimTestSuite("FireSim", "FireSimRocketChipConfig", "FireSimConfig") {
   runSuite("verilator")(NICLoopbackTests)
 }
+class RamModelRocketF1Tests extends FireSimTestSuite("FireSimNoNIC", "FireSimRocketChipDualCoreConfig", "Midas2Config")
+class RamModelBoomF1Tests extends FireSimTestSuite("FireBoomNoNIC", "FireSimBoomConfig", "Midas2Config")
diff --git a/sims/firesim b/sims/firesim
index 4cd75833..a3d48a43 160000
--- a/sims/firesim
+++ b/sims/firesim
@@ -1 +1 @@
-Subproject commit 4cd75833dfc1f9f796a1c5505ece6937fd253189
+Subproject commit a3d48a43a972e663e45a2ce4617a798a940d6a2b