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No-op barstools SFC compiler

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This commit is contained in:
abejgonzalez
2022-10-08 10:41:09 -07:00
parent 064c8be7bb
commit 2635bb4f80
2 changed files with 27 additions and 210 deletions
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88
src/main/scala/barstools/tapeout/transforms/GenerateTopAndHarness.scala
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@@ -13,46 +13,28 @@ import logger.LazyLogging
// Requires two phases, one to collect modules below synTop in the hierarchy
// and a second to remove those modules to generate the test harness
private class GenerateTopAndHarness(annotations: AnnotationSeq) extends LazyLogging {
val synTop: Option[String] = annotations.collectFirst { case SynTopAnnotation(s) => s }
val topFir: Option[String] = annotations.collectFirst { case TopFirAnnotation(s) => s }
val harnessFir: Option[String] = annotations.collectFirst { case HarnessFirAnnotation(s) => s }
val topAnnoOut: Option[String] = annotations.collectFirst { case TopAnnoOutAnnotation(s) => s }
val harnessAnnoOut: Option[String] = annotations.collectFirst { case HarnessAnnoOutAnnotation(s) => s }
val harnessTop: Option[String] = annotations.collectFirst { case HarnessTopAnnotation(h) => h }
val harnessConf: Option[String] = annotations.collectFirst { case HarnessConfAnnotation(h) => h }
val harnessOutput: Option[String] = annotations.collectFirst { case HarnessOutputAnnotation(h) => h }
val topDotfOut: Option[String] = annotations.collectFirst { case TopDotfOutAnnotation(h) => h }
val harnessDotfOut: Option[String] = annotations.collectFirst { case HarnessDotfOutAnnotation(h) => h }
val annoFiles: List[String] = annotations.flatMap {
case InputAnnotationFileAnnotation(f) => Some(f)
case _ => None
}.toList
lazy val rootCircuitTarget = CircuitTarget(harnessTop.get)
val topAnnos = synTop.map(st => ReParentCircuitAnnotation(rootCircuitTarget.module(st))) ++
topDotfOut.map(BlackBoxResourceFileNameAnno)
val outFir: Option[String] = annotations.collectFirst { case OutFirAnnotation(s) => s }
val outAnno: Option[String] = annotations.collectFirst { case OutAnnoAnnotation(s) => s }
// Dump firrtl and annotation files
protected def dump(
circuit: Circuit,
annotations: AnnotationSeq,
firFile: Option[String],
annoFile: Option[String]
): Unit = {
firFile.foreach { firPath =>
outFir.foreach { firPath =>
val outputFile = new java.io.PrintWriter(firPath)
outputFile.write(circuit.serialize)
outputFile.close()
}
annoFile.foreach { annoPath =>
outAnno.foreach { annoPath =>
val outputFile = new java.io.PrintWriter(annoPath)
outputFile.write(JsonProtocol.serialize(annotations.filter(_ match {
case _: DeletedAnnotation => false
case _: EmittedComponent => false
case _: EmittedAnnotation[_] => false
case _: FirrtlCircuitAnnotation => false
case _: OutAnnoAnnotation => false
case _: OutFirAnnotation => false
case _ => true
})))
outputFile.close()
@@ -60,65 +42,15 @@ private class GenerateTopAndHarness(annotations: AnnotationSeq) extends LazyLogg
}
// Top Generation
def executeTop(): Seq[ExtModule] = {
val annos = new FirrtlStage().execute(
Array.empty,
annotations ++ Seq(
RunFirrtlTransformAnnotation(Dependency[ReParentCircuit]),
RunFirrtlTransformAnnotation(Dependency[RemoveUnusedModules])
) ++
topAnnos
)
def executeTop(): Unit = {
val annos = new FirrtlStage().execute(Array.empty, annotations)
annos.collectFirst { case FirrtlCircuitAnnotation(circuit) => circuit } match {
case Some(circuit) =>
dump(circuit, annos, topFir, topAnnoOut)
circuit.modules.collect { case e: ExtModule => e }
case _ =>
throw new Exception(s"executeTop failed while executing FIRRTL!\n")
}
}
// Top and harness generation
def executeTopAndHarness(): Unit = {
// Execute top and get list of ExtModules to avoid collisions
val topExtModules = executeTop()
// order is determined by DependencyAPIMigration
val harnessAnnos =
harnessDotfOut.map(BlackBoxResourceFileNameAnno).toSeq ++
harnessTop.map(ht => ModuleNameSuffixAnnotation(rootCircuitTarget, s"_in${ht}")) ++
synTop.map(st => ConvertToExtModAnnotation(rootCircuitTarget.module(st))) ++
Seq(
LinkExtModulesAnnotation(topExtModules),
RunFirrtlTransformAnnotation(Dependency[ConvertToExtMod]),
RunFirrtlTransformAnnotation(Dependency[RemoveUnusedModules]),
RunFirrtlTransformAnnotation(Dependency[AvoidExtModuleCollisions]),
RunFirrtlTransformAnnotation(Dependency[AddSuffixToModuleNames])
)
// For harness run, change some firrtlOptions (below) for harness phase
// customTransforms: setup harness transforms, add AvoidExtModuleCollisions
// outputFileNameOverride: change to harnessOutput
// conf file must change to harnessConf by mapping annotations
val generatorAnnotations = annotations
.filterNot(_.isInstanceOf[OutputFileAnnotation])
.map {
case ReplSeqMemAnnotation(i, _) => ReplSeqMemAnnotation(i, harnessConf.get)
case HarnessOutputAnnotation(s) => OutputFileAnnotation(s)
case anno => anno
} ++ harnessAnnos
val annos = new FirrtlStage().execute(Array.empty, generatorAnnotations)
annos.collectFirst { case FirrtlCircuitAnnotation(circuit) => circuit } match {
case Some(circuit) =>
dump(circuit, annos, harnessFir, harnessAnnoOut)
dump(circuit, annos)
case _ =>
throw new Exception(s"executeTop failed while executing FIRRTL!\n")
}
}
}
object GenerateTop extends StageMain(new TapeoutStage(doHarness = false))
object GenerateTopAndHarness extends StageMain(new TapeoutStage(doHarness = true))
object GenerateTop extends StageMain(new TapeoutStage)