Initial outline of FPGA prototyping docs

This commit is contained in:
abejgonzalez
2020-11-05 17:06:34 -08:00
parent 083f34ab23
commit 255e88fe8f
5 changed files with 107 additions and 6 deletions

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@@ -106,12 +106,12 @@ Software
Sims
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**verilator (Verilator wrapper)**
**Verilator**
Verilator is an open source Verilog simulator.
The ``verilator`` directory provides wrappers which construct Verilator-based simulators from relevant generated RTL, allowing for execution of test RISC-V programs on the simulator (including vcd waveform files).
See :ref:`Verilator (Open-Source)` for more information.
**vcs (VCS wrapper)**
**VCS**
VCS is a proprietary Verilog simulator.
Assuming the user has valid VCS licenses and installations, the ``vcs`` directory provides wrappers which construct VCS-based simulators from relevant generated RTL, allowing for execution of test RISC-V programs on the simulator (including vcd/vpd waveform files).
See :ref:`Synopsys VCS (License Required)` for more information.
@@ -124,6 +124,13 @@ Sims
In order to use FireSim, the repository must be cloned and executed on AWS instances.
See :ref:`FireSim` for more information.
**FPGA Prototyping**
FPGA prototyping is supported in Chipyard using SiFive's ``fpga-shells``.
Some examples of FPGA's supported are Arty and VCU118.
For more accurate and deterministic simulation results, please consider using the :ref:`FireSim` platform.
See :ref:`FPGA Prototyping` for more information.
VLSI
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