From 252f9c6a121889367f1c86354fab8710be1a37c1 Mon Sep 17 00:00:00 2001
From: dunn <dunn@eecs.berkeley.edu>
Date: Wed, 7 Oct 2020 11:55:16 -0700
Subject: [PATCH] Beginning to modify Arty TestHarness to conform with
 HarnessBinders. Currently does not compile; debugging.

---
 fpga/src/main/scala/arty/TestHarness.scala    | 25 +++++++++++++++----
 .../chipyard/src/main/scala/DigitalTop.scala  |  3 ---
 2 files changed, 20 insertions(+), 8 deletions(-)

diff --git a/fpga/src/main/scala/arty/TestHarness.scala b/fpga/src/main/scala/arty/TestHarness.scala
index 8f0b7143..cd327243 100644
--- a/fpga/src/main/scala/arty/TestHarness.scala
+++ b/fpga/src/main/scala/arty/TestHarness.scala
@@ -2,13 +2,25 @@ package chipyard.fpga.arty
 
 import chisel3._
 import chisel3.experimental.{Analog}
-
+import scala.collection.mutable.{ArrayBuffer}
 import freechips.rocketchip.diplomacy.{LazyModule}
-import freechips.rocketchip.config.{Parameters}
-
+import freechips.rocketchip.config.{Field, Parameters}
 import sifive.fpgashells.shell.xilinx.artyshell.{ArtyShell}
-
 import chipyard.{BuildTop, HasHarnessSignalReferences}
+import chipyard.harness.{ApplyHarnessBinders, HarnessBinders}
+
+trait HasTestHarnessFunctions {
+  val lazySystem: LazyModule
+  val harnessFunctions = ArrayBuffer.empty[HasHarnessSignalReferences => Seq[Any]]
+  val portMap = scala.collection.mutable.Map[String, Seq[Data]]()
+}
+
+trait HasHarnessSignalReferences {
+  def harnessClock: Clock
+  def harnessReset: Reset
+  def dutReset: Reset
+  def success: Bool
+}
 
 class ArtyFPGATestHarness(override implicit val p: Parameters) extends ArtyShell with HasHarnessSignalReferences {
 
@@ -29,6 +41,9 @@ class ArtyFPGATestHarness(override implicit val p: Parameters) extends ArtyShell
   val dutReset = reset_core
 
   // must be after HasHarnessSignalReferences assignments
-  ldut.harnessFunctions.foreach(_(this))
+  ldut match { case d: HasTestHarnessFunctions =>
+    d.harnessFunctions.foreach(_(this))
+    ApplyHarnessBinders(this, d.lazySystem, p(HarnessBinders), d.portMap.toMap)
+  }
 }
 
diff --git a/generators/chipyard/src/main/scala/DigitalTop.scala b/generators/chipyard/src/main/scala/DigitalTop.scala
index 868286eb..c0ac1ff7 100644
--- a/generators/chipyard/src/main/scala/DigitalTop.scala
+++ b/generators/chipyard/src/main/scala/DigitalTop.scala
@@ -32,12 +32,9 @@ class DigitalTop(implicit p: Parameters) extends ChipyardSystem
 
 class DigitalTopModule[+L <: DigitalTop](l: L) extends ChipyardSystemModule(l)
   with testchipip.CanHaveTraceIOModuleImp
-  with testchipip.CanHavePeripheryBlockDeviceModuleImp
-  with testchipip.CanHavePeripherySerialModuleImp
   with sifive.blocks.devices.uart.HasPeripheryUARTModuleImp
   with sifive.blocks.devices.gpio.HasPeripheryGPIOModuleImp
   with sifive.blocks.devices.spi.HasPeripherySPIFlashModuleImp
-  with icenet.CanHavePeripheryIceNICModuleImp
   with chipyard.example.CanHavePeripheryGCDModuleImp
   with freechips.rocketchip.util.DontTouch
 // DOC include end: DigitalTop