add documentation on ring network and system bus

docs/Customization/Memory-Hierarchy.rst

@@ -38,6 +38,20 @@ Note that these configurations fully remove the L2 cache and mbus.
 This configuration fully removes the L2 cache and memory bus by setting the
 number of channels and number of banks to 0.
 
+The System Bus
+--------------
+
+The system bus is the TileLink network that sits between the tiles and the L2
+agents and MMIO peripherals. Ordinarily, it is a fully-connected crossbar,
+but TestChipIP provides a version that uses a ring network instead. This can
+be useful when taping out larger systems. To use  the ring network system
+bus, simply add the ``WithRingSystemBus`` config fragment to your configuration.
+
+.. literalinclude:: ../../generators/chipyard/src/main/scala/config/RocketConfigs.scala
+    :language: scala
+    :start-after: DOC include start: RingSystemBusRocket
+    :end-before: DOC include end: RingSystemBusRocket
+
 The SiFive L2 Cache
 -------------------
 

docs/Generators/TestChipIP.rst

@@ -3,7 +3,8 @@ Test Chip IP
 
 Chipyard includes a Test Chip IP library which provides various hardware
 widgets that may be useful when designing SoCs. This includes a :ref:`Serial Adapter`,
-:ref:`Block Device Controller`, :ref:`TileLink SERDES`, :ref:`TileLink Switcher`, and :ref:`UART Adapter`.
+:ref:`Block Device Controller`, :ref:`TileLink SERDES`, :ref:`TileLink Switcher`,
+:ref:`TileLink Ring Network`, and :ref:`UART Adapter`.
 
 Serial Adapter
 --------------
@@ -60,6 +61,19 @@ the select signal once TileLink messages have begun sending.
 For an example of how to use the switcher, take a look at the ``SwitcherTest``
 unit test in the `Test Chip IP unit tests <https://github.com/ucb-bar/testchipip/blob/master/src/main/scala/Unittests.scala>`_.
 
+TileLink Ring Network
+---------------------
+
+TestChipIP provides a TLRingNetwork generator that has a similar interface
+to the TLXbar provided by RocketChip, but uses ring networks internally rather
+than crossbars. This can be useful for chips with very wide TileLink networks
+(many cores and L2 banks) that can sacrifice cross-section bandwidth to relieve
+wire routing congestion. Documentation on how to use the ring network can be
+found in :ref:`The System Bus`. The implementation itself can be found 
+`here <https://github.com/ucb-bar/testchipip/blob/master/src/main/scala/Ring.scala>`_,
+and may serve as an example of how to implement your own TileLink network with
+a different topology.
+
 UART Adapter
 ------------