diff --git a/.gitmodules b/.gitmodules
index c4a9b2b9..88096baf 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -113,3 +113,6 @@
 [submodule "software/firemarshal"]
 	path = software/firemarshal
 	url = https://github.com/firesim/FireMarshal.git
+[submodule "tools/DRAMSim2"]
+	path = tools/DRAMSim2
+	url = https://github.com/firesim/DRAMSim2.git
diff --git a/build.sbt b/build.sbt
index 678fffb5..0a4e2167 100644
--- a/build.sbt
+++ b/build.sbt
@@ -127,7 +127,7 @@ lazy val chipyard = conditionalDependsOn(project in file("generators/chipyard"))
   .settings(commonSettings)
 
 lazy val tracegen = conditionalDependsOn(project in file("generators/tracegen"))
-  .dependsOn(rocketchip, sifive_cache, boom)
+  .dependsOn(rocketchip, sifive_cache, boom, utilities)
   .settings(commonSettings)
 
 lazy val utilities = conditionalDependsOn(project in file("generators/utilities"))
diff --git a/common.mk b/common.mk
index 1fd7a193..08e872f2 100644
--- a/common.mk
+++ b/common.mk
@@ -129,7 +129,7 @@ $(output_dir)/%.run: $(output_dir)/% $(sim)
 	(set -o pipefail && $(sim) $(PERMISSIVE_ON) +max-cycles=$(timeout_cycles) $(SIM_FLAGS) $(PERMISSIVE_OFF) $< </dev/null | tee $<.log) && touch $@
 
 $(output_dir)/%.out: $(output_dir)/% $(sim)
-	(set -o pipefail && $(sim) $(PERMISSIVE_ON) +max-cycles=$(timeout_cycles) $(VERBOSE_FLAGS) $(PERMISSIVE_OFF) $< </dev/null 2> >(spike-dasm > $@) | tee $<.log)
+	(set -o pipefail && $(sim) $(PERMISSIVE_ON) +dramsim +max-cycles=$(timeout_cycles) $(VERBOSE_FLAGS) $(PERMISSIVE_OFF) $< </dev/null 2> >(spike-dasm > $@) | tee $<.log)
 
 #########################################################################################
 # include build/project specific makefrags made from the generator
@@ -156,4 +156,10 @@ $(output_dir)/tracegen.result: $(output_dir)/tracegen.out $(AXE)
 
 tracegen: $(output_dir)/tracegen.result
 
+dramsim_dir = $(base_dir)/tools/DRAMSim2
+dramsim_lib = $(dramsim_dir)/libdramsim.a
+
+$(dramsim_lib):
+	$(MAKE) -C $(dramsim_dir) $(notdir $@)
+
 .PHONY: tracegen
diff --git a/generators/chipyard/src/main/scala/BoomConfigs.scala b/generators/chipyard/src/main/scala/BoomConfigs.scala
index cd1e691b..bda5cccd 100644
--- a/generators/chipyard/src/main/scala/BoomConfigs.scala
+++ b/generators/chipyard/src/main/scala/BoomConfigs.scala
@@ -12,7 +12,7 @@ import freechips.rocketchip.config.{Config}
 class SmallBoomConfig extends Config(
   new chipyard.iobinders.WithUARTAdapter ++                      // display UART with a SimUARTAdapter
   new chipyard.iobinders.WithTieOffInterrupts ++                 // tie off top-level interrupts
-  new chipyard.iobinders.WithSimAXIMem ++                        // drive the master AXI4 memory with a SimAXIMem
+  new chipyard.iobinders.WithBlackBoxSimMem ++                        // drive the master AXI4 memory with a SimAXIMem
   new chipyard.iobinders.WithTiedOffDebug ++                     // tie off debug (since we are using SimSerial for testing)
   new chipyard.iobinders.WithSimSerial ++                        // drive TSI with SimSerial for testing
   new testchipip.WithTSI ++                                      // use testchipip serial offchip link
@@ -32,7 +32,7 @@ class SmallBoomConfig extends Config(
 class MediumBoomConfig extends Config(
   new chipyard.iobinders.WithUARTAdapter ++
   new chipyard.iobinders.WithTieOffInterrupts ++
-  new chipyard.iobinders.WithSimAXIMem ++
+  new chipyard.iobinders.WithBlackBoxSimMem ++
   new chipyard.iobinders.WithTiedOffDebug ++
   new chipyard.iobinders.WithSimSerial ++
   new testchipip.WithTSI ++
@@ -51,7 +51,7 @@ class MediumBoomConfig extends Config(
 class LargeBoomConfig extends Config(
   new chipyard.iobinders.WithUARTAdapter ++
   new chipyard.iobinders.WithTieOffInterrupts ++
-  new chipyard.iobinders.WithSimAXIMem ++
+  new chipyard.iobinders.WithBlackBoxSimMem ++
   new chipyard.iobinders.WithTiedOffDebug ++
   new chipyard.iobinders.WithSimSerial ++
   new testchipip.WithTSI ++
@@ -70,7 +70,7 @@ class LargeBoomConfig extends Config(
 class MegaBoomConfig extends Config(
   new chipyard.iobinders.WithUARTAdapter ++
   new chipyard.iobinders.WithTieOffInterrupts ++
-  new chipyard.iobinders.WithSimAXIMem ++
+  new chipyard.iobinders.WithBlackBoxSimMem ++
   new chipyard.iobinders.WithTiedOffDebug ++
   new chipyard.iobinders.WithSimSerial ++
   new testchipip.WithTSI ++
@@ -89,7 +89,7 @@ class MegaBoomConfig extends Config(
 class DualSmallBoomConfig extends Config(
   new chipyard.iobinders.WithUARTAdapter ++
   new chipyard.iobinders.WithTieOffInterrupts ++
-  new chipyard.iobinders.WithSimAXIMem ++
+  new chipyard.iobinders.WithBlackBoxSimMem ++
   new chipyard.iobinders.WithTiedOffDebug ++
   new chipyard.iobinders.WithSimSerial ++
   new testchipip.WithTSI ++
@@ -108,7 +108,7 @@ class DualSmallBoomConfig extends Config(
 class SmallRV32BoomConfig extends Config(
   new chipyard.iobinders.WithUARTAdapter ++
   new chipyard.iobinders.WithTieOffInterrupts ++
-  new chipyard.iobinders.WithSimAXIMem ++
+  new chipyard.iobinders.WithBlackBoxSimMem ++
   new chipyard.iobinders.WithTiedOffDebug ++
   new chipyard.iobinders.WithSimSerial ++
   new testchipip.WithTSI ++
@@ -129,7 +129,7 @@ class SmallRV32BoomConfig extends Config(
 class HwachaLargeBoomConfig extends Config(
   new chipyard.iobinders.WithUARTAdapter ++
   new chipyard.iobinders.WithTieOffInterrupts ++
-  new chipyard.iobinders.WithSimAXIMem ++
+  new chipyard.iobinders.WithBlackBoxSimMem ++
   new chipyard.iobinders.WithTiedOffDebug ++
   new chipyard.iobinders.WithSimSerial ++
   new testchipip.WithTSI ++
@@ -149,7 +149,7 @@ class HwachaLargeBoomConfig extends Config(
 class LoopbackNICLargeBoomConfig extends Config(
   new chipyard.iobinders.WithUARTAdapter ++
   new chipyard.iobinders.WithTieOffInterrupts ++
-  new chipyard.iobinders.WithSimAXIMem ++
+  new chipyard.iobinders.WithBlackBoxSimMem ++
   new chipyard.iobinders.WithTiedOffDebug ++
   new chipyard.iobinders.WithSimSerial ++
   new chipyard.iobinders.WithLoopbackNIC ++                        // drive NIC IOs with loopback
diff --git a/generators/chipyard/src/main/scala/HeteroConfigs.scala b/generators/chipyard/src/main/scala/HeteroConfigs.scala
index b5cc6b8c..c275433f 100644
--- a/generators/chipyard/src/main/scala/HeteroConfigs.scala
+++ b/generators/chipyard/src/main/scala/HeteroConfigs.scala
@@ -11,7 +11,7 @@ import freechips.rocketchip.config.{Config}
 class LargeBoomAndRocketConfig extends Config(
   new chipyard.iobinders.WithUARTAdapter ++                      // display UART with a SimUARTAdapter
   new chipyard.iobinders.WithTieOffInterrupts ++                 // tie off top-level interrupts
-  new chipyard.iobinders.WithSimAXIMem ++                        // drive the master AXI4 memory with a SimAXIMem
+  new chipyard.iobinders.WithBlackBoxSimMem ++                        // drive the master AXI4 memory with a SimAXIMem
   new chipyard.iobinders.WithTiedOffDebug ++                     // tie off debug (since we are using SimSerial for testing)
   new chipyard.iobinders.WithSimSerial ++                        // drive TSI with SimSerial for testing
   new testchipip.WithTSI ++                                      // use testchipip serial offchip link
@@ -33,7 +33,7 @@ class LargeBoomAndRocketConfig extends Config(
 class HwachaLargeBoomAndHwachaRocketConfig extends Config(
   new chipyard.iobinders.WithUARTAdapter ++
   new chipyard.iobinders.WithTieOffInterrupts ++
-  new chipyard.iobinders.WithSimAXIMem ++
+  new chipyard.iobinders.WithBlackBoxSimMem ++
   new chipyard.iobinders.WithTiedOffDebug ++
   new chipyard.iobinders.WithSimSerial ++
   new testchipip.WithTSI ++
@@ -56,7 +56,7 @@ class HwachaLargeBoomAndHwachaRocketConfig extends Config(
 class DualLargeBoomAndRocketConfig extends Config(
   new chipyard.iobinders.WithUARTAdapter ++
   new chipyard.iobinders.WithTieOffInterrupts ++
-  new chipyard.iobinders.WithSimAXIMem ++
+  new chipyard.iobinders.WithBlackBoxSimMem ++
   new chipyard.iobinders.WithTiedOffDebug ++
   new chipyard.iobinders.WithSimSerial ++
   new testchipip.WithTSI ++
@@ -79,7 +79,7 @@ class DualLargeBoomAndRocketConfig extends Config(
 class LargeBoomAndHwachaRocketConfig extends Config(
   new chipyard.iobinders.WithUARTAdapter ++
   new chipyard.iobinders.WithTieOffInterrupts ++
-  new chipyard.iobinders.WithSimAXIMem ++
+  new chipyard.iobinders.WithBlackBoxSimMem ++
   new chipyard.iobinders.WithTiedOffDebug ++
   new chipyard.iobinders.WithSimSerial ++
   new testchipip.WithTSI ++
@@ -105,7 +105,7 @@ class LargeBoomAndHwachaRocketConfig extends Config(
 class LargeBoomAndRV32RocketConfig extends Config(
   new chipyard.iobinders.WithUARTAdapter ++
   new chipyard.iobinders.WithTieOffInterrupts ++
-  new chipyard.iobinders.WithSimAXIMem ++
+  new chipyard.iobinders.WithBlackBoxSimMem ++
   new chipyard.iobinders.WithTiedOffDebug ++
   new chipyard.iobinders.WithSimSerial ++
   new testchipip.WithTSI ++
@@ -129,7 +129,7 @@ class LargeBoomAndRV32RocketConfig extends Config(
 class DualLargeBoomAndDualRocketConfig extends Config(
   new chipyard.iobinders.WithUARTAdapter ++
   new chipyard.iobinders.WithTieOffInterrupts ++
-  new chipyard.iobinders.WithSimAXIMem ++
+  new chipyard.iobinders.WithBlackBoxSimMem ++
   new chipyard.iobinders.WithTiedOffDebug ++
   new chipyard.iobinders.WithSimSerial ++
   new testchipip.WithTSI ++
@@ -151,7 +151,7 @@ class DualLargeBoomAndDualRocketConfig extends Config(
 class LargeBoomAndRocketWithControlCoreConfig extends Config(
   new chipyard.iobinders.WithUARTAdapter ++
   new chipyard.iobinders.WithTieOffInterrupts ++
-  new chipyard.iobinders.WithSimAXIMem ++
+  new chipyard.iobinders.WithBlackBoxSimMem ++
   new chipyard.iobinders.WithTiedOffDebug ++
   new chipyard.iobinders.WithSimSerial ++
   new testchipip.WithTSI ++
diff --git a/generators/chipyard/src/main/scala/IOBinders.scala b/generators/chipyard/src/main/scala/IOBinders.scala
index 22715aaf..938ecc5f 100644
--- a/generators/chipyard/src/main/scala/IOBinders.scala
+++ b/generators/chipyard/src/main/scala/IOBinders.scala
@@ -103,6 +103,21 @@ class WithSimAXIMem extends OverrideIOBinder({
 })
 // DOC include end: WithSimAXIMem
 
+class WithBlackBoxSimMem extends OverrideIOBinder({
+  (clock, reset, _, top: CanHaveMasterAXI4MemPortModuleImp) => {
+    (top.mem_axi4 zip top.outer.memAXI4Node).foreach { case (io, node) =>
+      val memSize = top.p(ExtMem).get.master.size
+      val lineSize = top.p(CacheBlockBytes)
+      (io zip node.in).foreach { case (axi4, (_, edge)) =>
+        val mem = Module(new SimDRAM(memSize, lineSize, edge.bundle))
+        mem.io.axi <> axi4
+        mem.io.clock := clock
+        mem.io.reset := reset
+      }
+    }; Nil
+  }
+})
+
 class WithSimAXIMMIO extends OverrideIOBinder({
   (c, r, s, top: CanHaveMasterAXI4MMIOPortModuleImp) => top.connectSimAXIMMIO(); Nil
 })
diff --git a/generators/chipyard/src/main/scala/RocketConfigs.scala b/generators/chipyard/src/main/scala/RocketConfigs.scala
index 2e0f856a..c596dc29 100644
--- a/generators/chipyard/src/main/scala/RocketConfigs.scala
+++ b/generators/chipyard/src/main/scala/RocketConfigs.scala
@@ -11,7 +11,7 @@ import freechips.rocketchip.config.{Config}
 class RocketConfig extends Config(
   new chipyard.iobinders.WithUARTAdapter ++                      // display UART with a SimUARTAdapter
   new chipyard.iobinders.WithTieOffInterrupts ++                 // tie off top-level interrupts
-  new chipyard.iobinders.WithSimAXIMem ++                        // drive the master AXI4 memory with a SimAXIMem
+  new chipyard.iobinders.WithBlackBoxSimMem ++                        // drive the master AXI4 memory with a SimAXIMem
   new chipyard.iobinders.WithTiedOffDebug ++                     // tie off debug (since we are using SimSerial for testing)
   new chipyard.iobinders.WithSimSerial ++                        // drive TSI with SimSerial for testing
   new testchipip.WithTSI ++                                      // use testchipip serial offchip link
@@ -29,7 +29,7 @@ class RocketConfig extends Config(
 class HwachaRocketConfig extends Config(
   new chipyard.iobinders.WithUARTAdapter ++
   new chipyard.iobinders.WithTieOffInterrupts ++
-  new chipyard.iobinders.WithSimAXIMem ++
+  new chipyard.iobinders.WithBlackBoxSimMem ++
   new chipyard.iobinders.WithTiedOffDebug ++
   new chipyard.iobinders.WithSimSerial ++
   new testchipip.WithTSI ++
@@ -49,7 +49,7 @@ class HwachaRocketConfig extends Config(
 class GemminiRocketConfig extends Config(
   new chipyard.iobinders.WithUARTAdapter ++
   new chipyard.iobinders.WithTieOffInterrupts ++
-  new chipyard.iobinders.WithSimAXIMem ++
+  new chipyard.iobinders.WithBlackBoxSimMem ++
   new chipyard.iobinders.WithTiedOffDebug ++
   new chipyard.iobinders.WithSimSerial ++
   new testchipip.WithTSI ++
@@ -69,7 +69,7 @@ class GemminiRocketConfig extends Config(
 class RoccRocketConfig extends Config(
   new chipyard.iobinders.WithUARTAdapter ++
   new chipyard.iobinders.WithTieOffInterrupts ++
-  new chipyard.iobinders.WithSimAXIMem ++
+  new chipyard.iobinders.WithBlackBoxSimMem ++
   new chipyard.iobinders.WithTiedOffDebug ++
   new chipyard.iobinders.WithSimSerial ++
   new testchipip.WithTSI ++
@@ -89,7 +89,7 @@ class RoccRocketConfig extends Config(
 class jtagRocketConfig extends Config(
   new chipyard.iobinders.WithUARTAdapter ++
   new chipyard.iobinders.WithTieOffInterrupts ++
-  new chipyard.iobinders.WithSimAXIMem ++
+  new chipyard.iobinders.WithBlackBoxSimMem ++
   new chipyard.iobinders.WithSimDebug ++    // add SimJtag and SimSerial, use both to drive sim
   new chipyard.iobinders.WithSimSerial ++
   new testchipip.WithTSI ++
@@ -110,7 +110,7 @@ class jtagRocketConfig extends Config(
 class dmiRocketConfig extends Config(
   new chipyard.iobinders.WithUARTAdapter ++
   new chipyard.iobinders.WithTieOffInterrupts ++
-  new chipyard.iobinders.WithSimAXIMem ++
+  new chipyard.iobinders.WithBlackBoxSimMem ++
   new chipyard.iobinders.WithTiedOffSerial ++
   new chipyard.iobinders.WithSimDebug ++               // add SimDebug and use it to drive simulation
   new chipyard.config.WithNoGPIO ++
@@ -129,7 +129,7 @@ class dmiRocketConfig extends Config(
 class GCDTLRocketConfig extends Config(
   new chipyard.iobinders.WithUARTAdapter ++
   new chipyard.iobinders.WithTieOffInterrupts ++
-  new chipyard.iobinders.WithSimAXIMem ++
+  new chipyard.iobinders.WithBlackBoxSimMem ++
   new chipyard.iobinders.WithTiedOffDebug ++
   new chipyard.iobinders.WithSimSerial ++
   new testchipip.WithTSI ++
@@ -150,7 +150,7 @@ class GCDTLRocketConfig extends Config(
 class GCDAXI4BlackBoxRocketConfig extends Config(
   new chipyard.iobinders.WithUARTAdapter ++
   new chipyard.iobinders.WithTieOffInterrupts ++
-  new chipyard.iobinders.WithSimAXIMem ++
+  new chipyard.iobinders.WithBlackBoxSimMem ++
   new chipyard.iobinders.WithTiedOffDebug ++
   new chipyard.iobinders.WithSimSerial ++
   new testchipip.WithTSI ++
@@ -170,7 +170,7 @@ class GCDAXI4BlackBoxRocketConfig extends Config(
 class SimBlockDeviceRocketConfig extends Config(
   new chipyard.iobinders.WithUARTAdapter ++
   new chipyard.iobinders.WithTieOffInterrupts ++
-  new chipyard.iobinders.WithSimAXIMem ++
+  new chipyard.iobinders.WithBlackBoxSimMem ++
   new chipyard.iobinders.WithTiedOffDebug ++
   new chipyard.iobinders.WithSimSerial ++
   new chipyard.iobinders.WithSimBlockDevice ++             // drive block-device IOs with SimBlockDevice
@@ -190,7 +190,7 @@ class SimBlockDeviceRocketConfig extends Config(
 class BlockDeviceModelRocketConfig extends Config(
   new chipyard.iobinders.WithUARTAdapter ++
   new chipyard.iobinders.WithTieOffInterrupts ++
-  new chipyard.iobinders.WithSimAXIMem ++
+  new chipyard.iobinders.WithBlackBoxSimMem ++
   new chipyard.iobinders.WithTiedOffDebug ++
   new chipyard.iobinders.WithSimSerial ++
   new chipyard.iobinders.WithBlockDeviceModel ++           // drive block-device IOs with a BlockDeviceModel
@@ -211,7 +211,7 @@ class BlockDeviceModelRocketConfig extends Config(
 class GPIORocketConfig extends Config(
   new chipyard.iobinders.WithUARTAdapter ++
   new chipyard.iobinders.WithTieOffInterrupts ++
-  new chipyard.iobinders.WithSimAXIMem ++
+  new chipyard.iobinders.WithBlackBoxSimMem ++
   new chipyard.iobinders.WithTiedOffDebug ++
   new chipyard.iobinders.WithSimSerial ++
   new chipyard.iobinders.WithGPIOTiedOff ++                // tie off GPIO inputs into the top
@@ -231,7 +231,7 @@ class GPIORocketConfig extends Config(
 class QuadRocketConfig extends Config(
   new chipyard.iobinders.WithUARTAdapter ++
   new chipyard.iobinders.WithTieOffInterrupts ++
-  new chipyard.iobinders.WithSimAXIMem ++
+  new chipyard.iobinders.WithBlackBoxSimMem ++
   new chipyard.iobinders.WithTiedOffDebug ++
   new chipyard.iobinders.WithSimSerial ++
   new testchipip.WithTSI ++
@@ -249,7 +249,7 @@ class QuadRocketConfig extends Config(
 class RV32RocketConfig extends Config(
   new chipyard.iobinders.WithUARTAdapter ++
   new chipyard.iobinders.WithTieOffInterrupts ++
-  new chipyard.iobinders.WithSimAXIMem ++
+  new chipyard.iobinders.WithBlackBoxSimMem ++
   new chipyard.iobinders.WithTiedOffDebug ++
   new chipyard.iobinders.WithSimSerial ++
   new testchipip.WithTSI ++
@@ -267,7 +267,7 @@ class RV32RocketConfig extends Config(
 class GB1MemoryRocketConfig extends Config(
   new chipyard.iobinders.WithUARTAdapter ++
   new chipyard.iobinders.WithTieOffInterrupts ++
-  new chipyard.iobinders.WithSimAXIMem ++
+  new chipyard.iobinders.WithBlackBoxSimMem ++
   new chipyard.iobinders.WithTiedOffDebug ++
   new chipyard.iobinders.WithSimSerial ++
   new testchipip.WithTSI ++
@@ -287,7 +287,7 @@ class GB1MemoryRocketConfig extends Config(
 class Sha3RocketConfig extends Config(
   new chipyard.iobinders.WithUARTAdapter ++
   new chipyard.iobinders.WithTieOffInterrupts ++
-  new chipyard.iobinders.WithSimAXIMem ++
+  new chipyard.iobinders.WithBlackBoxSimMem ++
   new chipyard.iobinders.WithTiedOffDebug ++
   new chipyard.iobinders.WithSimSerial ++
   new testchipip.WithTSI ++
@@ -308,7 +308,7 @@ class Sha3RocketConfig extends Config(
 class InitZeroRocketConfig extends Config(
   new chipyard.iobinders.WithUARTAdapter ++
   new chipyard.iobinders.WithTieOffInterrupts ++
-  new chipyard.iobinders.WithSimAXIMem ++
+  new chipyard.iobinders.WithBlackBoxSimMem ++
   new chipyard.iobinders.WithTiedOffDebug ++
   new chipyard.iobinders.WithSimSerial ++
   new testchipip.WithTSI ++
@@ -328,7 +328,7 @@ class InitZeroRocketConfig extends Config(
 class LoopbackNICRocketConfig extends Config(
   new chipyard.iobinders.WithUARTAdapter ++
   new chipyard.iobinders.WithTieOffInterrupts ++
-  new chipyard.iobinders.WithSimAXIMem ++
+  new chipyard.iobinders.WithBlackBoxSimMem ++
   new chipyard.iobinders.WithTiedOffDebug ++
   new chipyard.iobinders.WithSimSerial ++
   new chipyard.iobinders.WithLoopbackNIC ++                        // drive NIC IOs with loopback
diff --git a/generators/chipyard/src/main/scala/TracegenConfigs.scala b/generators/chipyard/src/main/scala/TracegenConfigs.scala
index 1e9be623..fccac401 100644
--- a/generators/chipyard/src/main/scala/TracegenConfigs.scala
+++ b/generators/chipyard/src/main/scala/TracegenConfigs.scala
@@ -6,21 +6,21 @@ import freechips.rocketchip.config.{Config}
 import freechips.rocketchip.rocket.{DCacheParams}
 
 class TraceGenConfig extends Config(
-  new chipyard.iobinders.WithSimAXIMem ++
+  new chipyard.iobinders.WithBlackBoxSimMem ++
   new chipyard.iobinders.WithTraceGenSuccessBinder ++
   new chipyard.config.WithTracegenTop ++
   new tracegen.WithTraceGen(List.fill(2) { DCacheParams(nMSHRs = 0, nSets = 16, nWays = 2) }) ++
   new freechips.rocketchip.system.BaseConfig)
 
 class NonBlockingTraceGenConfig extends Config(
-  new chipyard.iobinders.WithSimAXIMem ++
+  new chipyard.iobinders.WithBlackBoxSimMem ++
   new chipyard.iobinders.WithTraceGenSuccessBinder ++
   new chipyard.config.WithTracegenTop ++
   new tracegen.WithTraceGen(List.fill(2) { DCacheParams(nMSHRs = 2, nSets = 16, nWays = 2) }) ++
   new freechips.rocketchip.system.BaseConfig)
 
 class BoomTraceGenConfig extends Config(
-  new chipyard.iobinders.WithSimAXIMem ++
+  new chipyard.iobinders.WithBlackBoxSimMem ++
   new chipyard.iobinders.WithTraceGenSuccessBinder ++
   new chipyard.config.WithTracegenTop ++
   new tracegen.WithBoomTraceGen(List.fill(2) { DCacheParams(nMSHRs = 8, nSets = 16, nWays = 2) }) ++
@@ -28,7 +28,7 @@ class BoomTraceGenConfig extends Config(
   new freechips.rocketchip.system.BaseConfig)
 
 class NonBlockingTraceGenL2Config extends Config(
-  new chipyard.iobinders.WithSimAXIMem ++
+  new chipyard.iobinders.WithBlackBoxSimMem ++
   new chipyard.iobinders.WithTraceGenSuccessBinder ++
   new chipyard.config.WithTracegenTop ++
   new tracegen.WithL2TraceGen(List.fill(2)(DCacheParams(nMSHRs = 2, nSets = 16, nWays = 4))) ++
diff --git a/generators/testchipip b/generators/testchipip
index a3da53e8..f1b41df8 160000
--- a/generators/testchipip
+++ b/generators/testchipip
@@ -1 +1 @@
-Subproject commit a3da53e87ad890be37138e27e477eb9a563fa82e
+Subproject commit f1b41df80d12b35f8f514c3fb72775203a7edd2d
diff --git a/generators/utilities/src/main/resources/csrc/emulator.cc b/generators/utilities/src/main/resources/csrc/emulator.cc
index 1a4f4dd2..0e86b836 100644
--- a/generators/utilities/src/main/resources/csrc/emulator.cc
+++ b/generators/utilities/src/main/resources/csrc/emulator.cc
@@ -35,6 +35,7 @@
 extern tsi_t* tsi;
 extern dtm_t* dtm;
 extern remote_bitbang_t * jtag;
+extern int dramsim;
 
 static uint64_t trace_count = 0;
 bool verbose;
@@ -124,6 +125,8 @@ int main(int argc, char** argv)
   char ** htif_argv = NULL;
   int verilog_plusargs_legal = 1;
 
+  dramsim = 0;
+
   while (1) {
     static struct option long_options[] = {
       {"cycle-count", no_argument,       0, 'c' },
@@ -132,6 +135,7 @@ int main(int argc, char** argv)
       {"seed",        required_argument, 0, 's' },
       {"rbb-port",    required_argument, 0, 'r' },
       {"verbose",     no_argument,       0, 'V' },
+      {"dramsim",     no_argument,       0, 'D' },
 #if VM_TRACE
       {"vcd",         required_argument, 0, 'v' },
       {"dump-start",  required_argument, 0, 'x' },
@@ -140,9 +144,9 @@ int main(int argc, char** argv)
     };
     int option_index = 0;
 #if VM_TRACE
-    int c = getopt_long(argc, argv, "-chm:s:r:v:Vx:", long_options, &option_index);
+    int c = getopt_long(argc, argv, "-chm:s:r:v:Vx:D", long_options, &option_index);
 #else
-    int c = getopt_long(argc, argv, "-chm:s:r:V", long_options, &option_index);
+    int c = getopt_long(argc, argv, "-chm:s:r:VD", long_options, &option_index);
 #endif
     if (c == -1) break;
  retry:
@@ -155,6 +159,7 @@ int main(int argc, char** argv)
       case 's': random_seed = atoi(optarg); break;
       case 'r': rbb_port = atoi(optarg);    break;
       case 'V': verbose = true;             break;
+      case 'D': dramsim = 1;                break;
 #if VM_TRACE
       case 'v': {
         vcdfile = strcmp(optarg, "-") == 0 ? stdout : fopen(optarg, "w");
@@ -188,6 +193,8 @@ int main(int argc, char** argv)
 #endif
         else if (arg.substr(0, 12) == "+cycle-count")
           c = 'c';
+        else if (arg == "+dramsim")
+          c = 'D';
         // If we don't find a legacy '+' EMULATOR argument, it still could be
         // a VERILOG_PLUSARG and not an error.
         else if (verilog_plusargs_legal) {
diff --git a/generators/utilities/src/main/scala/Simulator.scala b/generators/utilities/src/main/scala/Simulator.scala
index b1b2c4c4..b2982db7 100644
--- a/generators/utilities/src/main/scala/Simulator.scala
+++ b/generators/utilities/src/main/scala/Simulator.scala
@@ -83,6 +83,11 @@ object GenerateSimFiles extends App with HasGenerateSimConfig {
   }
   def resources(sim: Simulator): Seq[String] = Seq(
     "/testchipip/csrc/SimSerial.cc",
+    "/testchipip/csrc/SimDRAM.cc",
+    "/testchipip/csrc/mm.h",
+    "/testchipip/csrc/mm.cc",
+    "/testchipip/csrc/mm_dramsim2.h",
+    "/testchipip/csrc/mm_dramsim2.cc",
     "/csrc/SimDTM.cc",
     "/csrc/SimJTAG.cc",
     "/csrc/remote_bitbang.h",
diff --git a/sims/vcs/.gitignore b/sims/vcs/.gitignore
index a0991ff4..c3e65b20 100644
--- a/sims/vcs/.gitignore
+++ b/sims/vcs/.gitignore
@@ -1,3 +1,4 @@
 *
 !.gitignore
 !Makefile
+!dramsim2_ini
diff --git a/sims/vcs/Makefile b/sims/vcs/Makefile
index 86c28f23..e5c6e1be 100644
--- a/sims/vcs/Makefile
+++ b/sims/vcs/Makefile
@@ -47,7 +47,9 @@ VCS = vcs -full64
 VCS_CC_OPTS = \
 	-CC "-I$(VCS_HOME)/include" \
 	-CC "-I$(RISCV)/include" \
+	-CC "-I$(dramsim_dir)" \
 	-CC "-std=c++11" \
+	$(dramsim_lib) \
 	$(RISCV)/lib/libfesvr.a
 
 VCS_NONCC_OPTS = \
@@ -78,11 +80,11 @@ VCS_OPTS = -notice -line $(VCS_CC_OPTS) $(VCS_NONCC_OPTS)
 #########################################################################################
 # vcs simulator rules
 #########################################################################################
-$(sim): $(sim_vsrcs) $(sim_common_files)
+$(sim): $(sim_vsrcs) $(sim_common_files) $(dramsim_lib)
 	rm -rf csrc && $(VCS) $(VCS_OPTS) -o $@ \
 	-debug_pp
 
-$(sim_debug) : $(sim_vsrcs) $(sim_common_files)
+$(sim_debug) : $(sim_vsrcs) $(sim_common_files) $(dramsim_lib)
 	rm -rf csrc && $(VCS) $(VCS_OPTS) -o $@ \
 	+define+DEBUG -debug_pp
 
diff --git a/sims/vcs/dramsim2_ini b/sims/vcs/dramsim2_ini
new file mode 120000
index 00000000..19d93477
--- /dev/null
+++ b/sims/vcs/dramsim2_ini
@@ -0,0 +1 @@
+../../generators/testchipip/src/main/resources/dramsim2_ini
\ No newline at end of file
diff --git a/sims/verilator/.gitignore b/sims/verilator/.gitignore
index afbfb95f..136aa28f 100644
--- a/sims/verilator/.gitignore
+++ b/sims/verilator/.gitignore
@@ -2,3 +2,4 @@
 !.gitignore
 !Makefile
 !verilator.mk
+!dramsim2_ini
diff --git a/sims/verilator/Makefile b/sims/verilator/Makefile
index caaba672..140f54fd 100644
--- a/sims/verilator/Makefile
+++ b/sims/verilator/Makefile
@@ -45,8 +45,8 @@ include $(sim_dir)/verilator.mk
 #########################################################################################
 VERILATOR := $(INSTALLED_VERILATOR) --cc --exe
 
-CXXFLAGS := $(CXXFLAGS) -O1 -std=c++11 -I$(RISCV)/include -D__STDC_FORMAT_MACROS
-LDFLAGS := $(LDFLAGS) -L$(RISCV)/lib -Wl,-rpath,$(RISCV)/lib -L$(sim_dir) -lfesvr -lpthread
+CXXFLAGS := $(CXXFLAGS) -O1 -std=c++11 -I$(RISCV)/include -I$(dramsim_dir) -D__STDC_FORMAT_MACROS
+LDFLAGS := $(LDFLAGS) -L$(RISCV)/lib -Wl,-rpath,$(RISCV)/lib -L$(dramsim_dir) -Wl,-rpath,$(dramsim_dir) -L$(sim_dir) -lfesvr -lpthread -ldramsim
 
 VERILATOR_CC_OPTS = \
 	-O3 \
@@ -97,10 +97,10 @@ $(model_mk_debug): $(sim_vsrcs) $(sim_common_files) $(INSTALLED_VERILATOR)
 #########################################################################################
 # invoke make to make verilator sim rules
 #########################################################################################
-$(sim): $(model_mk)
+$(sim): $(model_mk) $(dramsim_lib)
 	$(MAKE) VM_PARALLEL_BUILDS=1 -C $(model_dir) -f V$(VLOG_MODEL).mk
 
-$(sim_debug): $(model_mk_debug)
+$(sim_debug): $(model_mk_debug) $(dramsim_lib)
 	$(MAKE) VM_PARALLEL_BUILDS=1 -C $(model_dir_debug) -f V$(VLOG_MODEL).mk
 
 #########################################################################################
diff --git a/sims/verilator/dramsim2_ini b/sims/verilator/dramsim2_ini
new file mode 120000
index 00000000..19d93477
--- /dev/null
+++ b/sims/verilator/dramsim2_ini
@@ -0,0 +1 @@
+../../generators/testchipip/src/main/resources/dramsim2_ini
\ No newline at end of file
diff --git a/tools/DRAMSim2 b/tools/DRAMSim2
new file mode 160000
index 00000000..2ec7965b
--- /dev/null
+++ b/tools/DRAMSim2
@@ -0,0 +1 @@
+Subproject commit 2ec7965b2ee051aaff03d5db21c6709aea4dd24e