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Merge pull request #195 from ucb-bar/doc-update

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Quick Doc Fixes
This commit is contained in:
Abraham Gonzalez
2019-08-08 17:23:16 -07:00
committed by GitHub
parent a8103eca56 8ba73d13b8
commit 24d41deaba
5 changed files with 9 additions and 7 deletions
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1
docs/Chipyard-Basics/Building-A-Chip.rst
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@@ -2,4 +2,5 @@
Building A Chip Building A Chip
============================== ==============================
TODO TODO

1
docs/Customization/index.rst
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@@ -12,6 +12,7 @@ Hit next to get started!
.. toctree:: .. toctree::
:maxdepth: 2 :maxdepth: 2
:caption: Customization: :caption: Customization:
Heterogeneous-SoCs Heterogeneous-SoCs
Adding-An-Accelerator Adding-An-Accelerator
Memory-Hierarchy Memory-Hierarchy

2
docs/Quick-Start.rst
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@@ -21,7 +21,7 @@ We need to install the RISC-V toolchain in order to be able to run RISC-V progra
This will take about 20-30 minutes. You can expedite the process by setting a ``make`` environment variable to use parallel cores: ``export MAKEFLAGS=-j8``. This will take about 20-30 minutes. You can expedite the process by setting a ``make`` environment variable to use parallel cores: ``export MAKEFLAGS=-j8``.
To build the toolchains, you should run: To build the toolchains, you should run:
:: .. code-block:: shell
./scripts/build-toolchains.sh ./scripts/build-toolchains.sh

2
docs/Simulation/FPGA-Accelerated-Simulators.rst
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@@ -56,6 +56,7 @@ classes from other generator projects into FireChip. For example, assuming you C
config looks as following: config looks as following:
.. code-block:: scala .. code-block:: scala
class CustomConfig extends Config( class CustomConfig extends Config(
new WithInclusiveCache ++ new WithInclusiveCache ++
new myproject.MyCustomConfig ++ new myproject.MyCustomConfig ++
@@ -66,6 +67,7 @@ Then the equivalent FireChip config (in `generators/firechip/src/main/scala/Targ
will look as follows: will look as follows:
.. code-block:: scala .. code-block:: scala
class FireSimCustomConfig extends Config( class FireSimCustomConfig extends Config(
new WithBootROM ++ new WithBootROM ++
new WithPeripheryBusFrequency(BigInt(3200000000L)) ++ new WithPeripheryBusFrequency(BigInt(3200000000L)) ++

2
docs/index.rst
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@@ -10,10 +10,8 @@ Chipyard is a a framework for designing and evaluating full-system hardware usin
It is composed of a collection of tools and libraries designed to provide an intergration between open-source and commercial tools for the development of systems-on-chip. It is composed of a collection of tools and libraries designed to provide an intergration between open-source and commercial tools for the development of systems-on-chip.
New to Chipyard? Jump to the :ref:`Chipyard Basics` page for more info. New to Chipyard? Jump to the :ref:`Chipyard Basics` page for more info.
.. include:: Quick-Start.rst .. include:: Quick-Start.rst
.. toctree:: .. toctree::
:maxdepth: 3 :maxdepth: 3
:caption: Contents: :caption: Contents: