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Separate new sys_clk and ddr2 from TSI

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abejgonzalez
2020-11-08 17:49:32 -08:00
parent 38a6bae872
commit 244205e2b4
4 changed files with 39 additions and 127 deletions
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2
fpga/src/main/scala/vcu118/TestHarness.scala
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@@ -38,6 +38,8 @@ class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118S
val jtagBScan = Overlay(JTAGDebugBScanOverlayKey, new JTAGDebugBScanVCU118ShellPlacer(this, JTAGDebugBScanShellInput()))
val fmc = Overlay(PCIeOverlayKey, new PCIeVCU118FMCShellPlacer(this, PCIeShellInput()))
val edge = Overlay(PCIeOverlayKey, new PCIeVCU118EdgeShellPlacer(this, PCIeShellInput()))
val sys_clock2 = Overlay(ClockInputOverlayKey, new SysClock2VCU118ShellPlacer(this, ClockInputShellInput()))
val ddr2 = Overlay(DDROverlayKey, new DDR2VCU118ShellPlacer(this, DDRShellInput()))
val topDesign = LazyModule(p(BuildTop)(dp))