Merge remote-tracking branch 'upstream/main' into graphics

generators/chipyard/src/main/resources/csrc/cospike.cc

@@ -42,6 +42,7 @@ extern std::map<long long int, backing_data_t> backing_mem_data;
 
 typedef struct system_info_t {
   std::string isa;
+  int vlen;
   int pmpregions;
   uint64_t mem0_base;
   uint64_t mem0_size;
@@ -79,9 +80,9 @@ std::set<reg_t> magic_addrs;
 cfg_t* cfg;
 std::vector<std::shared_ptr<read_override_device_t>> read_override_devices;
 
-static std::vector<std::pair<reg_t, mem_t*>> make_mems(const std::vector<mem_cfg_t> &layout)
+static std::vector<std::pair<reg_t, abstract_mem_t*>> make_mems(const std::vector<mem_cfg_t> &layout)
 {
-  std::vector<std::pair<reg_t, mem_t*>> mems;
+  std::vector<std::pair<reg_t, abstract_mem_t*>> mems;
   mems.reserve(layout.size());
   for (const auto &cfg : layout) {
     mems.push_back(std::make_pair(cfg.get_base(), new mem_t(cfg.get_size())));
@@ -89,7 +90,7 @@ static std::vector<std::pair<reg_t, mem_t*>> make_mems(const std::vector<mem_cfg
   return mems;
 }
 
-extern "C" void cospike_set_sysinfo(char* isa, char* priv, int pmpregions,
+extern "C" void cospike_set_sysinfo(char* isa, int vlen, char* priv, int pmpregions,
                                     long long int mem0_base, long long int mem0_size,
                                     int nharts,
                                     char* bootrom
@@ -98,6 +99,7 @@ extern "C" void cospike_set_sysinfo(char* isa, char* priv, int pmpregions,
     info = new system_info_t;
     // technically the targets aren't zicntr compliant, but they implement the zicntr registers
     info->isa = std::string(isa) + "_zicntr";
+    info->vlen = vlen;
     info->priv = std::string(priv);
     info->pmpregions = pmpregions;
     info->mem0_base = mem0_base;
@@ -133,11 +135,12 @@ extern "C" void cospike_cosim(long long int cycle,
     for (int i = 0; i < info->nharts; i++)
       hartids.push_back(i);
 
+    std::string visa = "vlen:" + std::to_string(info->vlen ? info->vlen : 128) + ",elen:64";
     cfg = new cfg_t(std::make_pair(0, 0),
                     nullptr,
                     info->isa.c_str(),
                     info->priv.c_str(),
-                    "vlen:128,elen:64",
+                    visa.c_str(),
                     false,
                     endianness_little,
                     info->pmpregions,
@@ -147,7 +150,7 @@ extern "C" void cospike_cosim(long long int cycle,
                     0
                     );
 
-    std::vector<std::pair<reg_t, mem_t*>> mems = make_mems(cfg->mem_layout());
+    std::vector<std::pair<reg_t, abstract_mem_t*>> mems = make_mems(cfg->mem_layout());
 
     size_t default_boot_rom_size = 0x10000;
     size_t default_boot_rom_addr = 0x10000;
@@ -420,7 +423,8 @@ extern "C" void cospike_cosim(long long int cycle,
     bool scalar_wb = false;
     bool vector_wb = false;
     uint32_t vector_cnt = 0;
-
+    std::vector<reg_t> vector_rds;
+    
     for (auto &regwrite : log) {
 
       //TODO: scaling to multi issue reads?
@@ -446,15 +450,16 @@ extern "C" void cospike_cosim(long long int cycle,
                            lr_read ||
                            (tohost_addr && mem_read_addr == tohost_addr) ||
                            (fromhost_addr && mem_read_addr == fromhost_addr)));
+      //COSPIKE_PRINTF("register write type %d\n", type);
       // check the type is compliant with writeback first
       if ((type == 0 || type == 1))
         scalar_wb = true;
       if (type == 2) {
+        vector_rds.push_back(rd);
         vector_wb = true;
       }
       if (type == 3) continue;
 
-
       if ((rd != 0 && type == 0) || type == 1) {
         // Override reads from some CSRs
         uint64_t csr_addr = (insn >> 20) & 0xfff;
@@ -496,5 +501,8 @@ extern "C" void cospike_cosim(long long int cycle,
       //   exit(-1);
       // }
     }
+    for (auto &a : vector_rds) {
+      COSPIKE_PRINTF("vector writeback to v%d\n", a);
+    }
   }
 }

generators/chipyard/src/main/resources/vsrc/cospike.v

@@ -1,75 +1,77 @@
 import "DPI-C" function void cospike_set_sysinfo(
-						 input string  isa,
-						 input string  priv,
-						 input int     pmpregions,
-						 input longint mem0_base,
-						 input longint mem0_size,
-						 input int     nharts,
-						 input string  bootrom
-						 );
+                                                 input string  isa,
+                                                 input int     vlen,
+                                                 input string  priv,
+                                                 input int     pmpregions,
+                                                 input longint mem0_base,
+                                                 input longint mem0_size,
+                                                 input int     nharts,
+                                                 input string  bootrom
+                                                 );
 
 import "DPI-C" function void cospike_cosim(input longint cycle,
                                            input longint hartid,
-					   input bit	 has_wdata,
-					   input bit	 valid,
-					   input longint iaddr,
-					   input int	 insn,
-					   input bit	 raise_exception,
-					   input bit	 raise_interrupt,
-					   input longint cause,
-					   input longint wdata,
-					   input int	 priv
-					   );
+                                           input bit     has_wdata,
+                                           input bit     valid,
+                                           input longint iaddr,
+                                           input int     insn,
+                                           input bit     raise_exception,
+                                           input bit     raise_interrupt,
+                                           input longint cause,
+                                           input longint wdata,
+                                           input int     priv
+                                           );
 
 
 module SpikeCosim  #(
-		     parameter ISA,
-		     parameter PRIV,
-		     parameter PMPREGIONS,
-		     parameter MEM0_BASE,
-		     parameter MEM0_SIZE,
-		     parameter NHARTS,
-		     parameter BOOTROM) (
-					 input	      clock,
-					 input	      reset,
+                     parameter ISA,
+                     parameter PRIV,
+                     parameter VLEN,
+                     parameter PMPREGIONS,
+                     parameter MEM0_BASE,
+                     parameter MEM0_SIZE,
+                     parameter NHARTS,
+                     parameter BOOTROM) (
+                                         input        clock,
+                                         input        reset,
 
-					 input [63:0] cycle,
+                                         input [63:0] cycle,
 
-					 input [63:0] hartid,
+                                         input [63:0] hartid,
 
-					 input	      trace_0_valid,
-					 input [63:0] trace_0_iaddr,
-					 input [31:0] trace_0_insn,
-					 input	      trace_0_exception,
-					 input	      trace_0_interrupt,
-					 input [63:0] trace_0_cause,
-					 input	      trace_0_has_wdata,
-					 input [63:0] trace_0_wdata,
-					 input [2:0]  trace_0_priv,
+                                         input        trace_0_valid,
+                                         input [63:0] trace_0_iaddr,
+                                         input [31:0] trace_0_insn,
+                                         input        trace_0_exception,
+                                         input        trace_0_interrupt,
+                                         input [63:0] trace_0_cause,
+                                         input        trace_0_has_wdata,
+                                         input [63:0] trace_0_wdata,
+                                         input [2:0]  trace_0_priv,
 
-					 input	      trace_1_valid,
-					 input [63:0] trace_1_iaddr,
-					 input [31:0] trace_1_insn,
-					 input	      trace_1_exception,
-					 input	      trace_1_interrupt,
-					 input [63:0] trace_1_cause,
-					 input	      trace_1_has_wdata,
-					 input [63:0] trace_1_wdata,
-					 input [2:0]  trace_1_priv
-					 );
+                                         input        trace_1_valid,
+                                         input [63:0] trace_1_iaddr,
+                                         input [31:0] trace_1_insn,
+                                         input        trace_1_exception,
+                                         input        trace_1_interrupt,
+                                         input [63:0] trace_1_cause,
+                                         input        trace_1_has_wdata,
+                                         input [63:0] trace_1_wdata,
+                                         input [2:0]  trace_1_priv
+                                         );
 
    initial begin
-      cospike_set_sysinfo(ISA, PRIV, PMPREGIONS, MEM0_BASE, MEM0_SIZE, NHARTS, BOOTROM);
+      cospike_set_sysinfo(ISA, VLEN, PRIV, PMPREGIONS, MEM0_BASE, MEM0_SIZE, NHARTS, BOOTROM);
    end;
 
    always @(posedge clock) begin
       if (!reset) begin
-	 if (trace_0_valid || trace_0_exception || trace_0_cause) begin
-	    cospike_cosim(cycle, hartid, trace_0_has_wdata, trace_0_valid, trace_0_iaddr,
-			  trace_0_insn, trace_0_exception, trace_0_interrupt, trace_0_cause,
-			  trace_0_wdata, trace_0_priv);
-	 end
-	 if (trace_1_valid || trace_1_exception || trace_1_cause) begin
+         if (trace_0_valid || trace_0_exception || trace_0_cause) begin
+            cospike_cosim(cycle, hartid, trace_0_has_wdata, trace_0_valid, trace_0_iaddr,
+                          trace_0_insn, trace_0_exception, trace_0_interrupt, trace_0_cause,
+                          trace_0_wdata, trace_0_priv);
+         end
+         if (trace_1_valid || trace_1_exception || trace_1_cause) begin
 	    cospike_cosim(cycle, hartid, trace_1_has_wdata, trace_1_valid, trace_1_iaddr,
 			  trace_1_insn, trace_1_exception, trace_1_interrupt, trace_1_cause,
 			  trace_1_wdata, trace_1_priv);

generators/chipyard/src/main/scala/Cospike.scala

@@ -14,6 +14,7 @@ import testchipip.TileTraceIO
 
 case class SpikeCosimConfig(
   isa: String,
+  vlen: Int,
   priv: String,
   pmpregions: Int,
   mem0_base: BigInt,
@@ -25,6 +26,7 @@ case class SpikeCosimConfig(
 
 class SpikeCosim(cfg: SpikeCosimConfig) extends BlackBox(Map(
   "ISA" -> StringParam(cfg.isa),
+  "VLEN" -> IntParam(cfg.vlen),
   "PRIV" -> StringParam(cfg.priv),
   "PMPREGIONS" -> IntParam(cfg.pmpregions),
   "MEM0_BASE" -> IntParam(cfg.mem0_base),

generators/chipyard/src/main/scala/IOBinders.scala

@@ -225,6 +225,7 @@ class WithExtInterruptIOCells extends OverrideIOBinder({
       val (port: UInt, cells) = IOCell.generateIOFromSignal(system.interrupts, "ext_interrupts", system.p(IOCellKey), abstractResetAsAsync = true)
       (Seq(port), cells)
     } else {
+      system.interrupts := DontCare // why do I have to drive this 0-wide wire???
       (Nil, Nil)
     }
   }
@@ -442,4 +443,13 @@ class WithDontTouchPorts extends OverrideIOBinder({
   (system: DontTouch) => system.dontTouchPorts(); (Nil, Nil)
 })
 
-
+class WithNMITiedOff extends ComposeIOBinder({
+  (system: HasTilesModuleImp) => {
+    system.nmi.flatten.foreach { nmi =>
+      nmi.rnmi := false.B
+      nmi.rnmi_interrupt_vector := 0.U
+      nmi.rnmi_exception_vector := 0.U
+    }
+    (Nil, Nil)
+  }
+})

generators/chipyard/src/main/scala/config/AbstractConfig.scala

@@ -45,6 +45,7 @@ class AbstractConfig extends Config(
   new chipyard.iobinders.WithNICIOPunchthrough ++
   new chipyard.iobinders.WithTraceIOPunchthrough ++
   new chipyard.iobinders.WithUARTTSIPunchthrough ++
+  new chipyard.iobinders.WithNMITiedOff ++
 
   // By default, punch out IOs to the Harness
   new chipyard.clocking.WithPassthroughClockGenerator ++

generators/chipyard/src/main/scala/config/ChipConfigs.scala

@@ -17,7 +17,7 @@ class ChipLikeRocketConfig extends Config(
   //==================================
   // Set up tiles
   //==================================
-  new freechips.rocketchip.subsystem.WithAsynchronousRocketTiles(3, 3) ++    // Add rational crossings between RocketTile and uncore
+  new freechips.rocketchip.subsystem.WithAsynchronousRocketTiles(8, 3) ++    // Add async crossings between RocketTile and uncore
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++                     // 1 RocketTile
 
   //==================================

generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala

@@ -8,7 +8,7 @@ import org.chipsalliance.cde.config.{Config}
 import freechips.rocketchip.devices.tilelink.{BootROMLocated, PLICKey, CLINTKey}
 import freechips.rocketchip.devices.debug.{Debug, ExportDebug, DebugModuleKey, DMI, JtagDTMKey, JtagDTMConfig}
 import freechips.rocketchip.diplomacy.{AsynchronousCrossing}
-import freechips.rocketchip.stage.phases.TargetDirKey
+import chipyard.stage.phases.TargetDirKey
 import freechips.rocketchip.subsystem._
 import freechips.rocketchip.tile.{XLen}
 

generators/chipyard/src/main/scala/example/FlatChipTop.scala

@@ -141,5 +141,11 @@ class FlatChipTop(implicit p: Parameters) extends LazyModule {
     //==========================
     require(system.uarts.size == 1)
     val (uart_pad, uartIOCells) = IOCell.generateIOFromSignal(system.module.uart.head, "uart_0", p(IOCellKey))
+
+
+    //==========================
+    // External interrupts (tie off)
+    //==========================
+    system.module.interrupts := DontCare
   }
 }

generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala

@@ -3,7 +3,6 @@
 package chipyard.example
 
 import chisel3._
-import chisel3.experimental.FixedPoint
 import chisel3.util._
 import dspblocks._
 import dsptools.numbers._
@@ -12,6 +11,8 @@ import org.chipsalliance.cde.config.{Parameters, Field, Config}
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.tilelink._
 import freechips.rocketchip.subsystem._
+import fixedpoint._
+import fixedpoint.{fromIntToBinaryPoint, fromSIntToFixedPoint, fromUIntToFixedPoint}
 
 // FIR params
 case class GenericFIRParams(
@@ -56,7 +57,7 @@ object GenericFIRIO {
 
 // A generic FIR filter
 // DOC include start: GenericFIR chisel
-class GenericFIR[T<:Data:Ring](genIn:T, genOut:T, coeffs: Seq[T]) extends Module {
+class GenericFIR[T<:Data:Ring](genIn:T, genOut:T, coeffs: => Seq[T]) extends Module {
   val io = IO(GenericFIRIO(genIn, genOut))
 
   // Construct a vector of genericFIRDirectCells
@@ -139,7 +140,7 @@ abstract class GenericFIRBlock[D, U, EO, EI, B<:Data, T<:Data:Ring]
 (
   genIn: T,
   genOut: T,
-  coeffs: Seq[T]
+  coeffs: => Seq[T]
 )(implicit p: Parameters) extends DspBlock[D, U, EO, EI, B] {
   val streamNode = AXI4StreamIdentityNode()
   val mem = None
@@ -175,7 +176,7 @@ class TLGenericFIRBlock[T<:Data:Ring]
 (
   val genIn: T,
   val genOut: T,
-  coeffs: Seq[T]
+  coeffs: => Seq[T]
 )(implicit p: Parameters) extends
 GenericFIRBlock[TLClientPortParameters, TLManagerPortParameters, TLEdgeOut, TLEdgeIn, TLBundle, T](
     genIn, genOut, coeffs
@@ -183,7 +184,7 @@ GenericFIRBlock[TLClientPortParameters, TLManagerPortParameters, TLEdgeOut, TLEd
 // DOC include end: TLGenericFIRBlock chisel
 
 // DOC include start: TLGenericFIRChain chisel
-class TLGenericFIRChain[T<:Data:Ring] (genIn: T, genOut: T, coeffs: Seq[T], params: GenericFIRParams)(implicit p: Parameters)
+class TLGenericFIRChain[T<:Data:Ring] (genIn: T, genOut: T, coeffs: => Seq[T], params: GenericFIRParams)(implicit p: Parameters)
   extends TLChain(Seq(
     TLWriteQueue(params.depth, AddressSet(params.writeAddress, 0xff))(_),
     { implicit p: Parameters =>
@@ -201,7 +202,7 @@ trait CanHavePeripheryStreamingFIR extends BaseSubsystem {
       val streamingFIR = LazyModule(new TLGenericFIRChain(
         genIn = FixedPoint(8.W, 3.BP),
         genOut = FixedPoint(8.W, 3.BP),
-        coeffs = Seq(1.F(0.BP), 2.F(0.BP), 3.F(0.BP)),
+        coeffs = Seq(1.U.asFixedPoint(0.BP), 2.U.asFixedPoint(0.BP), 3.U.asFixedPoint(0.BP)),
         params = params))
       pbus.coupleTo("streamingFIR") { streamingFIR.mem.get := TLFIFOFixer() := TLFragmenter(pbus.beatBytes, pbus.blockBytes) := _ }
       Some(streamingFIR)

generators/chipyard/src/main/scala/harness/HarnessBinders.scala

@@ -365,6 +365,7 @@ class WithCospike extends ComposeHarnessBinder({
     val tiles = chipyardSystem.tiles
     val cfg = SpikeCosimConfig(
       isa = tiles.headOption.map(_.isaDTS).getOrElse(""),
+      vlen = tiles.headOption.map(_.tileParams.core.vLen).getOrElse(0),
       priv = tiles.headOption.map(t => if (t.usingUser) "MSU" else if (t.usingSupervisor) "MS" else "M").getOrElse(""),
       mem0_base = p(ExtMem).map(_.master.base).getOrElse(BigInt(0)),
       mem0_size = p(ExtMem).map(_.master.size).getOrElse(BigInt(0)),

generators/chipyard/src/main/scala/harness/HasHarnessInstantiators.scala

@@ -7,7 +7,7 @@ import freechips.rocketchip.diplomacy.{LazyModule}
 import org.chipsalliance.cde.config.{Field, Parameters, Config}
 import freechips.rocketchip.util.{ResetCatchAndSync}
 import freechips.rocketchip.prci.{ClockBundle, ClockBundleParameters, ClockSinkParameters, ClockParameters}
-import freechips.rocketchip.stage.phases.TargetDirKey
+import chipyard.stage.phases.TargetDirKey
 
 import chipyard.harness.{ApplyHarnessBinders, HarnessBinders}
 import chipyard.iobinders.HasIOBinders

generators/chipyard/src/main/scala/stage/ChipyardAnnotations.scala

@@ -3,8 +3,11 @@
 
 package chipyard.stage
 
-import freechips.rocketchip.stage.ConfigsAnnotation
-import firrtl.options.{HasShellOptions, ShellOption}
+import chisel3.experimental.BaseModule
+import firrtl.annotations.{Annotation, NoTargetAnnotation}
+import firrtl.options.{HasShellOptions, ShellOption, Unserializable}
+
+trait ChipyardOption extends Unserializable { this: Annotation => }
 
 /** This hijacks the existing ConfigAnnotation to accept the legacy _-delimited format  */
 private[stage] object UnderscoreDelimitedConfigsAnnotation extends HasShellOptions {
@@ -23,3 +26,41 @@ private[stage] object UnderscoreDelimitedConfigsAnnotation extends HasShellOptio
     )
   )
 }
+
+/** Paths to config classes */
+case class ConfigsAnnotation(configNames: Seq[String]) extends NoTargetAnnotation with ChipyardOption
+private[stage] object ConfigsAnnotation extends HasShellOptions {
+  override val options = Seq(
+    new ShellOption[Seq[String]](
+      longOption = "configs",
+      toAnnotationSeq = a => Seq(ConfigsAnnotation(a)),
+      helpText = "<comma-delimited configs>",
+      shortOption = Some("C")
+    )
+  )
+}
+
+case class TopModuleAnnotation(clazz: Class[_ <: Any]) extends NoTargetAnnotation with ChipyardOption
+private[stage] object TopModuleAnnotation extends HasShellOptions {
+  override val options = Seq(
+    new ShellOption[String](
+      longOption = "top-module",
+      toAnnotationSeq = a => Seq(TopModuleAnnotation(Class.forName(a).asInstanceOf[Class[_ <: BaseModule]])),
+      helpText = "<top module>",
+      shortOption = Some("T")
+    )
+  )
+}
+
+/** Optional base name for generated files' filenames */
+case class OutputBaseNameAnnotation(outputBaseName: String) extends NoTargetAnnotation with ChipyardOption
+private[stage] object OutputBaseNameAnnotation extends HasShellOptions {
+  override val options = Seq(
+    new ShellOption[String](
+      longOption = "name",
+      toAnnotationSeq = a => Seq(OutputBaseNameAnnotation(a)),
+      helpText = "<base name of output files>",
+      shortOption = Some("n")
+    )
+  )
+}

generators/chipyard/src/main/scala/stage/ChipyardCli.scala

@@ -9,6 +9,9 @@ trait ChipyardCli { this: Shell =>
 
   parser.note("Chipyard Generator Options")
   Seq(
+    TopModuleAnnotation,
+    ConfigsAnnotation,
+    OutputBaseNameAnnotation,
     UnderscoreDelimitedConfigsAnnotation
   ).foreach(_.addOptions(parser))
 }

generators/chipyard/src/main/scala/stage/ChipyardOptions.scala

@@ -0,0 +1,41 @@
+// See LICENSE
+
+package chipyard.stage
+
+class ChipyardOptions private[stage] (
+                                         val topModule:         Option[Class[_ <: Any]] = None,
+                                         val configNames:       Option[Seq[String]] = None,
+                                         val outputBaseName:    Option[String] = None) {
+
+  private[stage] def copy(
+                           topModule:         Option[Class[_ <: Any]] = topModule,
+                           configNames:       Option[Seq[String]] = configNames,
+                           outputBaseName:    Option[String] = outputBaseName,
+                         ): ChipyardOptions = {
+
+    new ChipyardOptions(
+      topModule=topModule,
+      configNames=configNames,
+      outputBaseName=outputBaseName,
+    )
+  }
+
+  lazy val topPackage: Option[String] = topModule match {
+    case Some(a) => Some(a.getPackage.getName)
+    case _ => None
+  }
+
+  lazy val configClass: Option[String] = configNames match {
+    case Some(names) =>
+      val classNames = names.map{ n => n.split('.').last }
+      Some(classNames.mkString("_"))
+    case _ => None
+  }
+
+  lazy val longName: Option[String] = outputBaseName match {
+    case Some(name) => Some(name)
+    case _ =>
+      if (!topPackage.isEmpty && !configClass.isEmpty) Some(s"${topPackage.get}.${configClass.get}") else None
+  }
+}
+

generators/chipyard/src/main/scala/stage/ChipyardStage.scala

@@ -7,25 +7,35 @@ import chisel3.stage.{ChiselCli, ChiselStage}
 import firrtl.options.PhaseManager.PhaseDependency
 import firrtl.options.{Phase, PreservesAll, Shell}
 import firrtl.stage.FirrtlCli
-import freechips.rocketchip.stage.RocketChipCli
-import freechips.rocketchip.system.RocketChipStage
 
 import firrtl.options.{Phase, PhaseManager, PreservesAll, Shell, Stage, StageError, StageMain, Dependency}
 import firrtl.options.phases.DeletedWrapper
 
+final class ChipyardChiselStage extends ChiselStage {
+
+  override val targets = Seq(
+    Dependency[chisel3.stage.phases.Checks],
+    Dependency[chisel3.stage.phases.Elaborate],
+    Dependency[chisel3.stage.phases.AddImplicitOutputFile],
+    Dependency[chisel3.stage.phases.AddImplicitOutputAnnotationFile],
+    Dependency[chisel3.stage.phases.MaybeAspectPhase],
+    Dependency[chisel3.stage.phases.Emitter],
+    Dependency[chisel3.stage.phases.Convert]
+  )
+
+}
+
 class ChipyardStage extends ChiselStage {
-  override val shell = new Shell("chipyard") with ChipyardCli with RocketChipCli with ChiselCli with FirrtlCli
+  override val shell = new Shell("chipyard") with ChipyardCli with ChiselCli with FirrtlCli
   override val targets: Seq[PhaseDependency] = Seq(
-    Dependency[freechips.rocketchip.stage.phases.Checks],
-    Dependency[freechips.rocketchip.stage.phases.TransformAnnotations],
-    Dependency[freechips.rocketchip.stage.phases.PreElaboration],
-    // Note: Dependency[RocketChiselStage] is not listed here because it is
-    // package private, however it is named as a prereq for the passes below.
-    Dependency[freechips.rocketchip.stage.phases.GenerateFirrtlAnnos],
-    Dependency[freechips.rocketchip.stage.phases.AddDefaultTests],
+    Dependency[chipyard.stage.phases.Checks],
+    Dependency[chipyard.stage.phases.TransformAnnotations],
+    Dependency[chipyard.stage.phases.PreElaboration],
+    Dependency[ChipyardChiselStage],
+    Dependency[chipyard.stage.phases.GenerateFirrtlAnnos],
     Dependency[chipyard.stage.phases.AddDefaultTests],
     Dependency[chipyard.stage.phases.GenerateTestSuiteMakefrags],
-    Dependency[freechips.rocketchip.stage.phases.GenerateArtefacts],
+    Dependency[chipyard.stage.phases.GenerateArtefacts],
   )
   override final def invalidates(a: Phase): Boolean = false
 }

generators/chipyard/src/main/scala/stage/StageUtils.scala

@@ -0,0 +1,48 @@
+// See LICENSE
+
+package chipyard.stage
+
+import java.io.{File, FileWriter}
+
+import org.chipsalliance.cde.config.{Config, Parameters}
+import chisel3.internal.firrtl.Circuit
+import freechips.rocketchip.util.{BlackBoxedROM, ROMGenerator}
+
+trait HasChipyardStageUtils {
+
+  def getConfig(fullConfigClassNames: Seq[String]): Config = {
+    new Config(fullConfigClassNames.foldRight(Parameters.empty) { case (currentName, config) =>
+      val currentConfig = try {
+        Class.forName(currentName).newInstance.asInstanceOf[Config]
+      } catch {
+        case e: java.lang.ClassNotFoundException =>
+          throw new Exception(s"""Unable to find part "$currentName" from "$fullConfigClassNames", did you misspell it or specify the wrong package path?""", e)
+      }
+      currentConfig ++ config
+    })
+  }
+
+  def enumerateROMs(circuit: Circuit): String = {
+    val res = new StringBuilder
+    val configs =
+      circuit.components flatMap { m =>
+        m.id match {
+          case rom: BlackBoxedROM => Some((rom.name, ROMGenerator.lookup(rom)))
+          case _ => None
+        }
+      }
+    configs foreach { case (name, c) =>
+      res append s"name ${name} depth ${c.depth} width ${c.width}\n"
+    }
+    res.toString
+  }
+
+  def writeOutputFile(targetDir: String, fname: String, contents: String): File = {
+    val f = new File(targetDir, fname)
+    val fw = new FileWriter(f)
+    fw.write(contents)
+    fw.close
+    f
+  }
+
+}

generators/chipyard/src/main/scala/stage/package.scala

@@ -0,0 +1,24 @@
+// See LICENSE
+
+package chipyard
+
+import firrtl.AnnotationSeq
+import firrtl.options.OptionsView
+
+package object stage {
+
+  implicit object ChipyardOptionsView extends OptionsView[ChipyardOptions] {
+
+    def view(annotations: AnnotationSeq): ChipyardOptions = annotations
+      .collect { case a: ChipyardOption => a }
+      .foldLeft(new ChipyardOptions()){ (c, x) =>
+        x match {
+          case TopModuleAnnotation(a)         => c.copy(topModule = Some(a))
+          case ConfigsAnnotation(a)           => c.copy(configNames = Some(a))
+          case OutputBaseNameAnnotation(a)    => c.copy(outputBaseName = Some(a))
+        }
+      }
+
+  }
+
+}

generators/chipyard/src/main/scala/stage/phases/AddDefaultTests.scala

@@ -10,25 +10,23 @@ import org.chipsalliance.cde.config.Parameters
 import chisel3.stage.phases.Elaborate
 import firrtl.AnnotationSeq
 import firrtl.annotations.{Annotation, NoTargetAnnotation}
-import firrtl.options.{Phase, PreservesAll, Dependency}
-import firrtl.options.Viewer.view
-import freechips.rocketchip.stage.RocketChipOptions
-import freechips.rocketchip.stage.phases.{RocketTestSuiteAnnotation}
+import firrtl.options._
+import firrtl.options.Viewer._
 import freechips.rocketchip.system.{RocketTestSuite, TestGeneration}
 import freechips.rocketchip.subsystem.{TilesLocated, InSubsystem}
-import freechips.rocketchip.util.HasRocketChipStageUtils
 import freechips.rocketchip.tile.XLen
 
 import chipyard.TestSuiteHelper
 import chipyard.TestSuitesKey
+import chipyard.stage._
 
-class AddDefaultTests extends Phase with HasRocketChipStageUtils {
-  // Make sure we run both after RocketChip's version of this phase, and Rocket Chip's annotation emission phase
-  // because the RocketTestSuiteAnnotation is not serializable (but is not marked as such).
-  override val prerequisites = Seq(
-    Dependency[freechips.rocketchip.stage.phases.GenerateFirrtlAnnos],
-    Dependency[freechips.rocketchip.stage.phases.AddDefaultTests])
-  override val dependents = Seq(Dependency[freechips.rocketchip.stage.phases.GenerateTestSuiteMakefrags])
+/** Annotation that contains a list of [[RocketTestSuite]]s to run */
+case class ChipyardTestSuiteAnnotation(tests: Seq[RocketTestSuite]) extends NoTargetAnnotation with Unserializable
+
+
+class AddDefaultTests extends Phase with PreservesAll[Phase] with HasChipyardStageUtils {
+  override val prerequisites = Seq(Dependency[ChipyardChiselStage])
+  override val dependents = Seq(Dependency[GenerateTestSuiteMakefrags])
 
   private def addTestSuiteAnnotations(implicit p: Parameters): Seq[Annotation] = {
     val annotations = mutable.ArrayBuffer[Annotation]()
@@ -40,18 +38,16 @@ class AddDefaultTests extends Phase with HasRocketChipStageUtils {
       // If a custom test suite is set up, use the custom test suite
       annotations += CustomMakefragSnippet(p(TestSuitesKey).apply(tileParams, suiteHelper, p))
 
-    RocketTestSuiteAnnotation(suiteHelper.suites.values.toSeq) +: annotations.toSeq
+    ChipyardTestSuiteAnnotation(suiteHelper.suites.values.toSeq) +: annotations.toSeq
   }
 
 
   override def transform(annotations: AnnotationSeq): AnnotationSeq = {
     val (testSuiteAnnos, oAnnos) = annotations.partition {
-      case RocketTestSuiteAnnotation(_)  => true
+      case ChipyardTestSuiteAnnotation(_)  => true
       case o => false
     }
-    implicit val p = getConfig(view[RocketChipOptions](annotations).configNames.get).toInstance
-    addTestSuiteAnnotations ++ oAnnos
+    implicit val p = getConfig(view[ChipyardOptions](annotations).configNames.get).toInstance
+    addTestSuiteAnnotations(p) ++ oAnnos
   }
-
-  override final def invalidates(a: Phase): Boolean = false
 }

generators/chipyard/src/main/scala/stage/phases/Checks.scala

@@ -0,0 +1,47 @@
+// See LICENSE
+
+package chipyard.stage.phases
+
+import firrtl.AnnotationSeq
+import firrtl.annotations.Annotation
+import firrtl.options.{OptionsException, Phase, PreservesAll, TargetDirAnnotation}
+import chipyard.stage._
+
+import scala.collection.mutable
+
+/** Checks for the correct type and number of command line arguments */
+class Checks extends Phase with PreservesAll[Phase] {
+
+  override def transform(annotations: AnnotationSeq): AnnotationSeq = {
+    val targetDir, topModule, configNames, outputBaseName = mutable.ListBuffer[Annotation]()
+
+    annotations.foreach {
+      case a: TargetDirAnnotation      => a +=: targetDir
+      case a: TopModuleAnnotation      => a +=: topModule
+      case a: ConfigsAnnotation        => a +=: configNames
+      case a: OutputBaseNameAnnotation => a +=: outputBaseName
+      case _ =>
+    }
+
+    def required(annoList: mutable.ListBuffer[Annotation], option: String): Unit = {
+      if (annoList.size != 1) {
+        throw new OptionsException(s"Exactly one $option required")
+      }
+    }
+
+    def optional(annoList: mutable.ListBuffer[Annotation], option: String): Unit = {
+      if (annoList.size > 1) {
+        throw new OptionsException(s"Too many $option options have been specified")
+      }
+    }
+
+    required(targetDir, "target directory")
+    required(topModule, "top module")
+    required(configNames, "configs string (','-delimited)")
+
+    optional(outputBaseName, "output base name")
+
+    annotations
+  }
+
+}

generators/chipyard/src/main/scala/stage/phases/GenerateArtefacts.scala

@@ -0,0 +1,26 @@
+// See LICENSE
+
+package chipyard.stage.phases
+
+import firrtl.AnnotationSeq
+import firrtl.options.{Dependency, Phase, PreservesAll, StageOptions}
+import firrtl.options.Viewer.view
+import chipyard.stage._
+import freechips.rocketchip.util.{ElaborationArtefacts}
+
+/** Writes [[ElaborationArtefacts]] into files */
+class GenerateArtefacts extends Phase with PreservesAll[Phase] with HasChipyardStageUtils {
+
+  override val prerequisites = Seq(Dependency[chipyard.stage.ChipyardChiselStage])
+
+  override def transform(annotations: AnnotationSeq): AnnotationSeq = {
+    val targetDir = view[StageOptions](annotations).targetDir
+
+    ElaborationArtefacts.files.foreach { case (extension, contents) =>
+      writeOutputFile(targetDir, s"${view[ChipyardOptions](annotations).longName.get}.${extension}", contents ())
+    }
+
+    annotations
+  }
+
+}

generators/chipyard/src/main/scala/stage/phases/GenerateFirrtlAnnos.scala

@@ -0,0 +1,36 @@
+// See LICENSE
+
+package chipyard.stage.phases
+
+import firrtl.AnnotationSeq
+import firrtl.annotations.{DeletedAnnotation, JsonProtocol}
+import firrtl.options.Viewer.view
+import firrtl.options._
+import chipyard.stage._
+
+/** Writes FIRRTL annotations into a file */
+class GenerateFirrtlAnnos extends Phase with PreservesAll[Phase] with HasChipyardStageUtils {
+
+  override val prerequisites = Seq(Dependency[chipyard.stage.ChipyardChiselStage])
+
+  override def transform(annotations: AnnotationSeq): AnnotationSeq = {
+    val targetDir = view[StageOptions](annotations).targetDir
+    val fileName = s"${view[ChipyardOptions](annotations).longName.get}.anno.json"
+
+    val annos = annotations.view.flatMap {
+      // Remove TargetDirAnnotation so that we can pass as argument to FIRRTL
+      // Remove CustomFileEmission, those are serialized automatically by Stages
+      case (_: Unserializable | _: TargetDirAnnotation | _: CustomFileEmission) =>
+        None
+      case DeletedAnnotation(_, (_: Unserializable | _: CustomFileEmission)) =>
+        None
+      case a =>
+        Some(a)
+    }
+
+    writeOutputFile(targetDir, fileName, JsonProtocol.serialize(annos.toSeq))
+
+    annotations
+  }
+
+}

generators/chipyard/src/main/scala/stage/phases/GenerateTestSuiteMakefrags.scala

@@ -9,10 +9,8 @@ import firrtl.AnnotationSeq
 import firrtl.annotations.{Annotation, NoTargetAnnotation}
 import firrtl.options.{Phase, PreservesAll, StageOptions, Unserializable, Dependency}
 import firrtl.options.Viewer.view
-import freechips.rocketchip.stage.RocketChipOptions
-import freechips.rocketchip.stage.phases.{RocketTestSuiteAnnotation}
+import chipyard.stage._
 import freechips.rocketchip.system.TestGeneration
-import freechips.rocketchip.util.HasRocketChipStageUtils
 
 trait MakefragSnippet { self: Annotation =>
   def toMakefrag: String
@@ -21,19 +19,19 @@ trait MakefragSnippet { self: Annotation =>
 case class CustomMakefragSnippet(val toMakefrag: String) extends NoTargetAnnotation with MakefragSnippet with Unserializable
 
 /** Generates a make script to run tests in [[RocketTestSuiteAnnotation]]. */
-class GenerateTestSuiteMakefrags extends Phase with HasRocketChipStageUtils {
+class GenerateTestSuiteMakefrags extends Phase with HasChipyardStageUtils {
 
   // Our annotations tend not to be serializable, but are not marked as such.
-  override val prerequisites = Seq(Dependency[freechips.rocketchip.stage.phases.GenerateFirrtlAnnos],
+  override val prerequisites = Seq(Dependency[chipyard.stage.phases.GenerateFirrtlAnnos],
                                    Dependency[chipyard.stage.phases.AddDefaultTests])
 
   override def transform(annotations: AnnotationSeq): AnnotationSeq = {
     val targetDir = view[StageOptions](annotations).targetDir
-    val fileName = s"${view[RocketChipOptions](annotations).longName.get}.d"
+    val fileName = s"${view[ChipyardOptions](annotations).longName.get}.d"
 
     val makefragBuilder = new mutable.StringBuilder()
     val outputAnnotations = annotations.flatMap {
-      case RocketTestSuiteAnnotation(tests) =>
+      case ChipyardTestSuiteAnnotation(tests) =>
         // Unfortunately the gen method of TestGeneration is rocketchip package
         // private, so we either have to copy code in or use the stateful form
         TestGeneration.addSuites(tests)

generators/chipyard/src/main/scala/stage/phases/PreElaboration.scala

@@ -0,0 +1,43 @@
+// See LICENSE
+
+package chipyard.stage.phases
+
+import chisel3.RawModule
+import chisel3.stage.ChiselGeneratorAnnotation
+import firrtl.AnnotationSeq
+import firrtl.options.Viewer.view
+import firrtl.options.{Dependency, Phase, PreservesAll, StageOptions}
+import org.chipsalliance.cde.config.{Field, Parameters}
+import freechips.rocketchip.diplomacy._
+import chipyard.stage._
+
+case object TargetDirKey extends Field[String](".")
+
+/** Constructs a generator function that returns a top module with given config parameters */
+class PreElaboration extends Phase with PreservesAll[Phase] with HasChipyardStageUtils {
+
+  override val prerequisites = Seq(Dependency[Checks])
+  override val dependents = Seq(Dependency[chisel3.stage.phases.Elaborate])
+
+  override def transform(annotations: AnnotationSeq): AnnotationSeq = {
+
+    val stageOpts = view[StageOptions](annotations)
+    val rOpts = view[ChipyardOptions](annotations)
+    val topMod = rOpts.topModule.get
+
+    val config = getConfig(rOpts.configNames.get).alterPartial {
+      case TargetDirKey => stageOpts.targetDir
+    }
+
+    val gen = () =>
+      topMod
+        .getConstructor(classOf[Parameters])
+        .newInstance(config) match {
+          case a: RawModule => a
+          case a: LazyModule => LazyModule(a).module
+        }
+
+    ChiselGeneratorAnnotation(gen) +: annotations
+  }
+
+}

generators/chipyard/src/main/scala/stage/phases/TransformAnnotations.scala

@@ -0,0 +1,21 @@
+// See LICENSE
+
+package chipyard.stage.phases
+
+import chisel3.stage.ChiselOutputFileAnnotation
+import firrtl.AnnotationSeq
+import firrtl.options.Viewer.view
+import firrtl.options.{Dependency, Phase, PreservesAll}
+import chipyard.stage._
+
+/** Transforms RocketChipAnnotations into those used by other stages */
+class TransformAnnotations extends Phase with PreservesAll[Phase] with HasChipyardStageUtils {
+
+  override val prerequisites = Seq(Dependency[Checks])
+  override val dependents = Seq(Dependency[chisel3.stage.phases.AddImplicitOutputFile])
+
+  override def transform(annotations: AnnotationSeq): AnnotationSeq = {
+    /** Construct output file annotation for emission */
+    new ChiselOutputFileAnnotation(view[ChipyardOptions](annotations).longName.get) +: annotations
+  }
+}

generators/chipyard/src/main/scala/upf/UPFAspect.scala

@@ -4,7 +4,7 @@ package chipyard.upf
 import chisel3.aop.{Aspect}
 import firrtl.{AnnotationSeq}
 import chipyard.harness.{TestHarness}
-import freechips.rocketchip.stage.phases.{TargetDirKey}
+import chipyard.stage.phases.{TargetDirKey}
 import freechips.rocketchip.diplomacy.{LazyModule}
 
 abstract class UPFAspect[T <: TestHarness](upf: UPFFunc.UPFFunction) extends Aspect[T] {