Merge branch 'dev' of github.com:ucb-bar/chipyard into verilator-makefile-fix

2020-09-25 20:33:05 -07:00
parent 700f68730b 023d8096a9
commit 23847a6dca
65 changed files with 1785 additions and 1336 deletions
--- a/sims/common-sim-flags.mk
+++ b/sims/common-sim-flags.mk
@@ -0,0 +1,23 @@
+#----------------------------------------------------------------------------------------
+# common gcc configuration/optimization
+#----------------------------------------------------------------------------------------
+SIM_OPT_CXXFLAGS := -O3
+
+SIM_CXXFLAGS = \
+	$(CXXFLAGS) \
+	$(SIM_OPT_CXXFLAGS) \
+	-std=c++11 \
+	-I$(RISCV)/include \
+	-I$(dramsim_dir) \
+	-I$(build_dir) \
+	$(EXTRA_SIM_CXXFLAGS)
+
+SIM_LDFLAGS = \
+	$(LDFLAGS) \
+	-L$(RISCV)/lib \
+	-Wl,-rpath,$(RISCV)/lib \
+	-L$(sim_dir) \
+	-L$(dramsim_dir) \
+	-lfesvr \
+	-ldramsim \
+	$(EXTRA_SIM_LDFLAGS)
--- a/sims/firesim
+++ b/sims/firesim
--- a/sims/vcs/Makefile
+++ b/sims/vcs/Makefile
@@ -41,16 +41,24 @@ include $(base_dir)/common.mk
 #########################################################################################
 VCS = vcs -full64

-VCS_OPTS = -notice -line $(VCS_CC_OPTS) $(VCS_NONCC_OPTS) $(VCS_DEFINE_OPTS) $(EXTRA_SIM_SOURCES)
+VCS_OPTS = $(VCS_CC_OPTS) $(VCS_NONCC_OPTS) $(PREPROC_DEFINES)
+
+#########################################################################################
+# vcs build paths
+#########################################################################################
+model_dir = $(build_dir)/$(long_name)
+model_dir_debug = $(build_dir)/$(long_name).debug

 #########################################################################################
 # vcs simulator rules
 #########################################################################################
 $(sim): $(sim_vsrcs) $(sim_common_files) $(dramsim_lib) $(EXTRA_SIM_REQS)
-	rm -rf csrc && $(VCS) $(VCS_OPTS) -o $@
+	rm -rf $(model_dir)
+	$(VCS) $(VCS_OPTS) $(EXTRA_SIM_SOURCES) -o $@ -Mdir=$(model_dir)

 $(sim_debug): $(sim_vsrcs) $(sim_common_files) $(dramsim_lib) $(EXTRA_SIM_REQS)
-	rm -rf csrc && $(VCS) $(VCS_OPTS) -o $@ \
+	rm -rf $(model_dir_debug)
+	$(VCS) $(VCS_OPTS) $(EXTRA_SIM_SOURCES) -o $@ -Mdir=$(model_dir_debug)  \
 	+define+DEBUG

 #########################################################################################
@@ -61,8 +69,14 @@ $(output_dir)/%.vpd: $(output_dir)/% $(sim_debug)
 	(set -o pipefail && $(sim_debug) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(VERBOSE_FLAGS) +vcdplusfile=$@ $(PERMISSIVE_OFF) $< </dev/null 2> >(spike-dasm > $<.out) | tee $<.log)

 #########################################################################################
-# general cleanup rule
+# general cleanup rules
 #########################################################################################
-.PHONY: clean
+.PHONY: clean clean-sim clean-sim-debug
 clean:
-	rm -rf $(gen_dir) csrc $(sim_prefix)-* ucli.key vc_hdrs.h
+	rm -rf $(gen_dir) $(sim_prefix)-* ucli.key
+
+clean-sim:
+	rm -rf $(model_dir) $(build_dir)/vc_hdrs.h $(sim) $(sim).daidir ucli.key
+
+clean-sim-debug:
+	rm -rf $(model_dir_debug) $(build_dir)/vc_hdrs.h $(sim_debug) $(sim_debug).daidir ucli.key
--- a/sims/verilator/Makefile
+++ b/sims/verilator/Makefile
@@ -22,7 +22,7 @@ include $(base_dir)/variables.mk
 sim_name = verilator

 #########################################################################################
-# vcs simulator types and rules
+# verilator simulator types and rules
 #########################################################################################
 sim_prefix = simulator
 sim = $(sim_dir)/$(sim_prefix)-$(MODEL_PACKAGE)-$(CONFIG)
@@ -47,35 +47,53 @@ debug: $(sim_debug)
 include $(base_dir)/common.mk

 #########################################################################################
-# verilator binary and flags
+# verilator-specific user-interface variables and commands
+#########################################################################################
+HELP_COMPILATION_VARIABLES += \
+"   VERILATOR_PROFILE      = 'none' if no verilator profiling (default)" \
+"                            'all' if full verilator runtime profiling" \
+"                            'threads' if runtime thread profiling only" \
+"   VERILATOR_THREADS      = how many threads the simulator will use (default 1)" \
+"   VERILATOR_FST_MODE     = enable FST waveform instead of VCD. use with debug build"
+
+#########################################################################################
+# verilator/cxx binary and flags
 #########################################################################################
 VERILATOR := verilator --cc --exe

-CXXFLAGS := \
-	$(CXXFLAGS) -O1 -std=c++11 \
-	-I$(RISCV)/include \
-	-I$(dramsim_dir) \
-	-D__STDC_FORMAT_MACROS \
-	$(EXTRA_SIM_CC_FLAGS)
+#----------------------------------------------------------------------------------------
+# user configs
+#----------------------------------------------------------------------------------------
+VERILATOR_PROFILE ?= none
+RUNTIME_PROFILING_CFLAGS := $(if $(filter $(VERILATOR_PROFILE),all),-g -pg,)
+RUNTIME_PROFILING_VFLAGS := $(if $(filter $(VERILATOR_PROFILE),all),\
+                              --prof-threads --prof-cfuncs,\
+                              $(if $(filter $(VERILATOR_PROFILE),threads),\
+								--prof-threads,))

-LDFLAGS := \
-	$(LDFLAGS) \
-	-L$(sim_dir) \
-	-lpthread
+VERILATOR_THREADS ?= 1
+RUNTIME_THREADS := --threads $(VERILATOR_THREADS) --threads-dpi all

-VERILATOR_CC_OPTS = \
+VERILATOR_FST_MODE ?= 0
+TRACING_OPTS := $(if $(filter $(VERILATOR_FST_MODE),0),\
+	                  --trace,--trace-fst --trace-threads 1)
+TRACING_CFLAGS := $(if $(filter $(VERILATOR_FST_MODE),0),,-DCY_FST_TRACE)
+
+#----------------------------------------------------------------------------------------
+# verilation configuration/optimization
+#----------------------------------------------------------------------------------------
+# we initially had --noassert for performance, but several modules use
+# assertions, including dramsim, so we enable --assert by default
+VERILATOR_OPT_FLAGS := \
 	-O3 \
-	-CFLAGS "$(CXXFLAGS) -DTEST_HARNESS=V$(VLOG_MODEL) -DVERILATOR" \
-	-CFLAGS "-I$(build_dir) -include $(build_dir)/$(long_name).plusArgs -include $(build_dir)/verilator.h" \
-	-LDFLAGS "$(LDFLAGS)" \
-	$(RISCV)/lib/libfesvr.a \
-	$(dramsim_lib)
+	--x-assign fast \
+	--x-initial fast \
+	--output-split 10000 \
+	--output-split-cfuncs 100

-# default flags added for ariane
-ARIANE_VERILATOR_FLAGS = \
+# default flags added for external IP (ariane/NVDLA)
+VERILOG_IP_VERILATOR_FLAGS := \
 	--unroll-count 256 \
-	-Werror-PINMISSING \
-	-Werror-IMPLICIT \
 	-Wno-PINCONNECTEMPTY \
 	-Wno-ASSIGNDLY \
 	-Wno-DECLFILENAME \
@@ -85,29 +103,66 @@ ARIANE_VERILATOR_FLAGS = \
 	-Wno-style \
 	-Wall

-# normal flags used for chipyard builds (that are incompatible with ariane)
-CHIPYARD_VERILATOR_FLAGS = \
+# normal flags used for chipyard builds (that are incompatible with vlog ip aka ariane/NVDLA)
+CHIPYARD_VERILATOR_FLAGS := \
 	--assert

+# options dependent on whether external IP (ariane/NVDLA) or just chipyard is used
+# NOTE: defer the evaluation of this until it is used!
+PLATFORM_OPTS = $(shell \
+	if grep -qiP "module\s+(Ariane|NVDLA)" $(build_dir)/*.*v; \
+	then echo "$(VERILOG_IP_VERILATOR_FLAGS)"; \
+	else echo "$(CHIPYARD_VERILATOR_FLAGS)"; fi)
+
 # Use --timescale to approximate timescale behavior of pre-4.034
 TIMESCALE_OPTS := $(shell verilator --version | perl -lne 'if (/(\d.\d+)/ && $$1 >= 4.034) { print "--timescale 1ns/1ps"; }')
-VERILATOR_NONCC_OPTS = \
-	$(TIMESCALE_OPTS) \
-	--top-module $(VLOG_MODEL) \
-	--vpi \
-	-Wno-fatal \
-	$(shell if ! grep -iq "module.*ariane" $(build_dir)/*.*v; then echo "$(CHIPYARD_VERILATOR_FLAGS)"; else echo "$(ARIANE_VERILATOR_FLAGS)"; fi) \
-	--output-split 10000 \
-	--output-split-cfuncs 100 \
-	--max-num-width 1048576 \
-	-f $(sim_common_files) \
-	$(sim_vsrcs)

-VERILATOR_DEFINES = \
+# see: https://github.com/ucb-bar/riscv-mini/issues/31
+MAX_WIDTH_OPTS = $(shell verilator --version | perl -lne 'if (/(\d.\d+)/ && $$1 > 4.016) { print "--max-num-width 1048576"; }')
+
+PREPROC_DEFINES := \
 	+define+PRINTF_COND=\$$c\(\"verbose\",\"\&\&\"\,\"done_reset\"\) \
 	+define+STOP_COND=\$$c\(\"done_reset\"\)

-VERILATOR_OPTS = $(VERILATOR_CC_OPTS) $(VERILATOR_NONCC_OPTS) $(VERILATOR_DEFINES) $(EXTRA_SIM_SOURCES)
+VERILATOR_NONCC_OPTS = \
+	$(RUNTIME_PROFILING_VFLAGS) \
+	$(RUNTIME_THREADS) \
+	$(VERILATOR_OPT_FLAGS) \
+	$(PLATFORM_OPTS) \
+	-Wno-fatal \
+	$(TIMESCALE_OPTS) \
+	$(MAX_WIDTH_OPTS) \
+	$(PREPROC_DEFINES) \
+	--top-module $(VLOG_MODEL) \
+	--vpi \
+	-f $(sim_common_files) \
+	$(sim_vsrcs)
+
+#----------------------------------------------------------------------------------------
+# gcc configuration/optimization
+#----------------------------------------------------------------------------------------
+include $(base_dir)/sims/common-sim-flags.mk
+
+VERILATOR_CXXFLAGS = \
+	$(SIM_CXXFLAGS) \
+	$(RUNTIME_PROFILING_CFLAGS) \
+	$(TRACING_CFLAGS) \
+	-D__STDC_FORMAT_MACROS \
+	-DTEST_HARNESS=V$(VLOG_MODEL) \
+	-DVERILATOR \
+	-include $(build_dir)/$(long_name).plusArgs \
+	-include $(build_dir)/verilator.h
+
+VERILATOR_LDFLAGS = $(SIM_LDFLAGS)
+
+VERILATOR_CC_OPTS = \
+	-CFLAGS "$(VERILATOR_CXXFLAGS)" \
+	-LDFLAGS "$(VERILATOR_LDFLAGS)"
+
+#----------------------------------------------------------------------------------------
+# full verilator+gcc opts
+#----------------------------------------------------------------------------------------
+VERILATOR_OPTS = $(VERILATOR_CC_OPTS) $(VERILATOR_NONCC_OPTS)

 #########################################################################################
 # verilator build paths and file names
@@ -127,13 +182,13 @@ model_mk_debug = $(model_dir_debug)/V$(VLOG_MODEL).mk
 $(model_mk): $(sim_vsrcs) $(sim_common_files) $(EXTRA_SIM_REQS)
 	rm -rf $(model_dir)
 	mkdir -p $(model_dir)
-	$(VERILATOR) $(VERILATOR_OPTS) -o $(sim) -Mdir $(model_dir) -CFLAGS "-include $(model_header)"
+	$(VERILATOR) $(VERILATOR_OPTS) $(EXTRA_SIM_SOURCES) -o $(sim) -Mdir $(model_dir) -CFLAGS "-include $(model_header)"
 	touch $@

 $(model_mk_debug): $(sim_vsrcs) $(sim_common_files) $(EXTRA_SIM_REQS)
 	rm -rf $(model_dir_debug)
 	mkdir -p $(model_dir_debug)
-	$(VERILATOR) $(VERILATOR_OPTS) -o $(sim_debug) --trace -Mdir $(model_dir_debug) -CFLAGS "-include $(model_header_debug)"
+	$(VERILATOR) $(VERILATOR_OPTS) $(EXTRA_SIM_SOURCES) -o $(sim_debug) $(TRACING_OPTS) -Mdir $(model_dir_debug) -CFLAGS "-include $(model_header_debug)"
 	touch $@

 #########################################################################################
@@ -152,11 +207,17 @@ $(sim_debug): $(model_mk_debug) $(dramsim_lib)
 $(output_dir)/%.vpd: $(output_dir)/% $(sim_debug)
 	rm -f $@.vcd && mkfifo $@.vcd
 	vcd2vpd $@.vcd $@ > /dev/null &
-	(set -o pipefail && $(sim_debug) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(SEED_FLAG) $(VERBOSE_FLAGS) -v$@.vcd $(PERMISSIVE_OFF) $< </dev/null 2> >(spike-dasm > $<.out) | tee $<.log)
+	(set -o pipefail && $(NUMA_PREFIX) $(sim_debug) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(SEED_FLAG) $(VERBOSE_FLAGS) -v$@.vcd $(PERMISSIVE_OFF) $< </dev/null 2> >(spike-dasm > $<.out) | tee $<.log)

 #########################################################################################
-# general cleanup rule
+# general cleanup rules
 #########################################################################################
-.PHONY: clean
+.PHONY: clean clean-sim clean-sim-debug
 clean:
 	rm -rf $(gen_dir) $(sim_prefix)-*
+
+clean-sim:
+	rm -rf $(model_dir) $(sim)
+
+clean-sim-debug:
+	rm -rf $(model_dir_debug) $(sim_debug)