wu-arch/chipyard
1
0
Fork 0
Code Issues Pull Requests Actions 1 Packages Projects Releases Wiki Activity

top blackbox isolation hack, bump submodules

Browse Source
This commit is contained in:
Harrison Liew
2023-02-02 18:24:28 -08:00
committed by abejgonzalez
parent a9f9f32078
commit 22834faa1f
5 changed files with 12 additions and 9 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
common.mk
View File

@@ -192,7 +192,7 @@ endif
--disable-annotation-classless \ --disable-annotation-classless \
--disable-annotation-unknown \ --disable-annotation-unknown \
--mlir-timing \ --mlir-timing \
--lowering-options=emittedLineLength=2048,noAlwaysComb,disallowLocalVariables,explicitBitcast,verifLabels,locationInfoStyle=wrapInAtSquareBracket \ --lowering-options=emittedLineLength=2048,noAlwaysComb,disallowPackedArrays,disallowLocalVariables,explicitBitcast,verifLabels,locationInfoStyle=wrapInAtSquareBracket \
--repl-seq-mem \ --repl-seq-mem \
--repl-seq-mem-file=$(MFC_SMEMS_CONF) \ --repl-seq-mem-file=$(MFC_SMEMS_CONF) \
--repl-seq-mem-circuit=$(MODEL) \ --repl-seq-mem-circuit=$(MODEL) \

14
vlsi/Makefile
View File

@@ -23,7 +23,7 @@ sim_name ?= vcs # needed for GenerateSimFiles, but is unused
tech_name ?= asap7 tech_name ?= asap7
tech_dir ?= $(if $(filter $(tech_name),sky130 asap7 nangate45),\ tech_dir ?= $(if $(filter $(tech_name),sky130 asap7 nangate45),\
$(site_packages_dir)/hammer/technology/$(tech_name), \ $(site_packages_dir)/hammer/technology/$(tech_name), \
$(vlsi_dir)/hammer-$(tech_name)-plugin/hammer/technology/$(tech_name)) $(vlsi_dir)/hammer-$(tech_name)-plugin/hammer/$(tech_name))
SMEMS_COMP ?= $(tech_dir)/sram-compiler.json SMEMS_COMP ?= $(tech_dir)/sram-compiler.json
SMEMS_CACHE ?= $(tech_dir)/sram-cache.json SMEMS_CACHE ?= $(tech_dir)/sram-cache.json
SMEMS_HAMMER ?= $(build_dir)/$(long_name).mems.hammer.json SMEMS_HAMMER ?= $(build_dir)/$(long_name).mems.hammer.json
@@ -55,12 +55,13 @@ endif
######################################################################################### #########################################################################################
# general rules # general rules
######################################################################################### #########################################################################################
# TODO: get all the top blackboxes only
extra_v_includes = $(build_dir)/EICG_wrapper.v $(build_dir)/gen-collateral/IOCell.v
ifneq ($(CUSTOM_VLOG), ) ifneq ($(CUSTOM_VLOG), )
VLSI_RTL = $(CUSTOM_VLOG) VLSI_RTL = $(CUSTOM_VLOG)
VLSI_BB =
else else
VLSI_RTL = $(shell cat $(TOP_MODS_FILELIST)) $(TOP_SMEMS_FILE) $(extra_v_includes) VLSI_RTL = $(shell cat $(TOP_MODS_FILELIST)) $(TOP_SMEMS_FILE)
# TODO: have MFC split top & harness blackboxes
VLSI_BB = $(build_dir)/EICG_wrapper.v $(shell rev $(BB_MODS_FILELIST) | sed -E 's/cc(.*)/c\1/g' | uniq -s 1 | sed '/c\./d' | rev)
endif endif
.PHONY: default .PHONY: default
@@ -122,6 +123,7 @@ $(SIM_CONF): $(sim_common_files)
mkdir -p $(dir $@) mkdir -p $(dir $@)
echo "sim.inputs:" > $@ echo "sim.inputs:" > $@
echo " top_module: $(VLSI_TOP)" >> $@ echo " top_module: $(VLSI_TOP)" >> $@
echo " tb_name: ''" >> $@ # don't specify -top
echo " input_files:" >> $@ echo " input_files:" >> $@
for x in $(shell cat $(sim_common_files)); do \ for x in $(shell cat $(sim_common_files)); do \
echo ' - "'$$x'"' >> $@; \ echo ' - "'$$x'"' >> $@; \
@@ -220,12 +222,12 @@ ifeq ($(CUSTOM_VLOG), )
GENERATED_CONFS += $(SRAM_CONF) GENERATED_CONFS += $(SRAM_CONF)
endif endif
$(SYN_CONF): $(VLSI_RTL) $(SYN_CONF): $(VLSI_RTL) $(VLSI_BB)
mkdir -p $(dir $@) mkdir -p $(dir $@)
echo "synthesis.inputs:" >> $@ echo "synthesis.inputs:" >> $@
echo " top_module: $(VLSI_TOP)" >> $@ echo " top_module: $(VLSI_TOP)" >> $@
echo " input_files:" >> $@ echo " input_files:" >> $@
for x in $(VLSI_RTL); do \ for x in $(VLSI_RTL) $(VLSI_BB); do \
echo ' - "'$$x'"' >> $@; \ echo ' - "'$$x'"' >> $@; \
done done

1
vlsi/example-openroad.yml
View File

@@ -1,4 +1,5 @@
# Tool options. Replace with your tool plugin of choice. # Tool options. Replace with your tool plugin of choice.
vlsi.core.build_system: make
# Yosys # Yosys
vlsi.core.synthesis_tool: "hammer.synthesis.yosys" vlsi.core.synthesis_tool: "hammer.synthesis.yosys"
# OpenROAD # OpenROAD

2
vlsi/hammer-cadence-plugins

Submodule vlsi/hammer-cadence-plugins updated: a33e4716f0...f9e323bd64

2
vlsi/hammer-synopsys-plugins

Submodule vlsi/hammer-synopsys-plugins updated: be9088128d...e080a48000