From 225cf9d29aa2fd0625bcb7b0dd8f28718929005a Mon Sep 17 00:00:00 2001 From: alonamid Date: Tue, 1 Jun 2021 16:40:31 -0700 Subject: [PATCH] update frequency config fragements --- .../src/main/scala/ConfigFragments.scala | 14 +++++ .../src/main/scala/config/RocketConfigs.scala | 5 ++ .../src/main/scala/TargetConfigs.scala | 59 ++++--------------- .../src/test/scala/ScalaTestSuite.scala | 8 +-- 4 files changed, 31 insertions(+), 55 deletions(-) diff --git a/generators/chipyard/src/main/scala/ConfigFragments.scala b/generators/chipyard/src/main/scala/ConfigFragments.scala index a36285eb..da4d9edf 100644 --- a/generators/chipyard/src/main/scala/ConfigFragments.scala +++ b/generators/chipyard/src/main/scala/ConfigFragments.scala @@ -319,3 +319,17 @@ class WithControlBusFrequency(freqMHz: Double) extends Config((site, here, up) = class WithRationalMemoryBusCrossing extends WithSbusToMbusCrossingType(RationalCrossing(Symmetric)) class WithAsynchrousMemoryBusCrossing extends WithSbusToMbusCrossingType(AsynchronousCrossing()) + +class WithTestChipBusFreqs extends Config( + // Frequency specifications + new chipyard.config.WithTileFrequency(1600.0) ++ // Matches the maximum frequency of U540 + new chipyard.config.WithSystemBusFrequency(800.0) ++ // Put the system bus at a lower freq, representative of ncore working at a lower frequency than the tiles. Same freq as U540 + new chipyard.config.WithMemoryBusFrequency(1000.0) ++ // 2x the U540 freq (appropriate for a 128b Mbus) + new chipyard.config.WithPeripheryBusFrequency(100) ++ // Retains the default pbus frequency + new chipyard.config.WithSystemBusFrequencyAsDefault ++ // All unspecified clock frequencies, notably the implicit clock, will use the sbus freq (800 MHz) + // Crossing specifications + new chipyard.config.WithCbusToPbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossing between PBUS and CBUS + new chipyard.config.WithSbusToMbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossings between backside of L2 and MBUS + new freechips.rocketchip.subsystem.WithRationalRocketTiles ++ // Add rational crossings between RocketTile and uncore + new testchipip.WithAsynchronousSerialSlaveCrossing // Add Async crossing between serial and MBUS. Its master-side is tied to the FBUS +) diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala index a81c1449..96257838 100644 --- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala +++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala @@ -207,6 +207,11 @@ class MulticlockRocketConfig extends Config( new testchipip.WithAsynchronousSerialSlaveCrossing ++ // Add Async crossing between serial and MBUS. Its master-side is tied to the FBUS new chipyard.config.AbstractConfig) +class TestChipMulticlockRocketConfig extends Config( + new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new chipyard.config.WithTestChipBusFreqs ++ + new chipyard.config.AbstractConfig) + class LBWIFRocketConfig extends Config( new testchipip.WithSerialTLMem(isMainMemory=true) ++ // set lbwif memory base to DRAM_BASE, use as main memory new freechips.rocketchip.subsystem.WithNoMemPort ++ // remove AXI4 backing memory diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala index 3da8ba94..be7845f5 100644 --- a/generators/firechip/src/main/scala/TargetConfigs.scala +++ b/generators/firechip/src/main/scala/TargetConfigs.scala @@ -50,6 +50,7 @@ class WithScalaTestFeatures extends Config((site, here, up) => { // FASED Config Aliases. This to enable config generation via "_" concatenation // which requires that all config classes be defined in the same package +class DDR3FCFS extends FCFS16GBQuadRank class DDR3FRFCFS extends FRFCFS16GBQuadRank class DDR3FRFCFSLLC4MB extends FRFCFS16GBQuadRankLLC4MB @@ -83,50 +84,14 @@ class WithFireSimDesignTweaks extends Config( new chipyard.config.WithNoDebug ) -// Tweaks to modify target clock frequencies / crossings to firesim defaults -class WithFireSimDefaultFrequencyTweaks extends Config( - // Optional: This sets the default frequency for all buses in the system to 2 GHz - // (since unspecified bus frequencies will use the pbus frequency) - new chipyard.config.WithPeripheryBusFrequency(2000.0) ++ - // Optional: These three configs will put the system bus at a frequency of 1 GHz - // Which is more representative of on uncore working at a lower frequency than the tiles - new chipyard.config.WithSystemBusFrequency(1000.0) ++ - new chipyard.config.WithSbusToCbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossing between SBUS and CBUS - new chipyard.config.WithFbusToSbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossing between FBUS and SBUS - // Optional: These three configs put the DRAM memory system in it's own clock domian. - // Removing the first config will result in the FASED timing model running - // at the pbus freq (above, 3.2 GHz), which is outside the range of valid DDR3 speedgrades. - // 1 GHz matches the FASED default, using some other frequency will require - // runnings the FASED runtime configuration generator to generate faithful DDR3 timing values. - new chipyard.config.WithMemoryBusFrequency(1000.0) ++ - new chipyard.config.WithAsynchrousMemoryBusCrossing ++ - new testchipip.WithAsynchronousSerialSlaveCrossing -) - -// Tweaks to modify target clock frequencies / crossings to testchip defaults -class WithFireSimTestchipFrequencyTweaks extends Config( - // Optional: This sets the default frequency for all buses in the system to 1 GHz - // (since unspecified bus frequencies will use the pbus frequency). - // This frequency is representative of Rocket/BOOM-based test chips - new chipyard.config.WithPeripheryBusFrequency(1000.0) ++ - // Optional: These three configs put the DRAM memory system in it's own clock domian. - // Removing the first config will result in the FASED timing model running - // at the pbus freq (above, 3.2 GHz), which is outside the range of valid DDR3 speedgrades. - // 1 GHz matches the FASED default, using some other frequency will require - // runnings the FASED runtime configuration generator to generate faithful DDR3 timing values. - new chipyard.config.WithMemoryBusFrequency(1000.0) ++ - new chipyard.config.WithAsynchrousMemoryBusCrossing ++ - new testchipip.WithAsynchronousSerialSlaveCrossing -) - // Tweaks to modify target clock frequencies / crossings to legacy firesim defaults -class WithFireSimHighPerfFrequencyTweaks extends Config( +class WithFireSimHighPerfClocking extends Config( // Optional: This sets the default frequency for all buses in the system to 3.2 GHz // (since unspecified bus frequencies will use the pbus frequency) // This frequency selection matches FireSim's legacy selection and is required // to support 200Gb NIC performance. You may select a smaller value. new chipyard.config.WithPeripheryBusFrequency(3200.0) ++ - // Optional: These three configs put the DRAM memory system in it's own clock domian. + // Optional: These three configs put the DRAM memory system in it's own clock domain. // Removing the first config will result in the FASED timing model running // at the pbus freq (above, 3.2 GHz), which is outside the range of valid DDR3 speedgrades. // 1 GHz matches the FASED default, using some other frequency will require @@ -136,21 +101,24 @@ class WithFireSimHighPerfFrequencyTweaks extends Config( new testchipip.WithAsynchronousSerialSlaveCrossing ) -// Tweaks that are generally applied to all firesim configs +// Tweaks that are generally applied to all firesim configs setting a single clock domain at 1000 MHz class WithFireSimConfigTweaks extends Config( - new WithFireSimDefaultFrequencyTweaks ++ + // 1 GHz matches the FASED default, using some other frequency will require + // runnings the FASED runtime configuration generator to generate faithful DDR3 timing values. + new chipyard.config.WithSystemBusFrequency(1000.0) ++ + new chipyard.config.WithSystemBusFrequencyAsDefault ++ // All unspecified clock frequencies, notably the implicit clock, will use the sbus freq (1000 MHz) new WithFireSimDesignTweaks ) // Tweak more representative of testchip configs -class WithFireSimTestchipConfigTweaks extends Config( - new WithFireSimTestchipFrequencyTweaks ++ +class WithFireSimTestChipConfigTweaks extends Config( + new chipyard.config.WithTestChipBusFreqs ++ new WithFireSimDesignTweaks ) // Tweaks for legacy FireSim configs. class WithFireSimHighPerfConfigTweaks extends Config( - new WithFireSimHighPerfFrequencyTweaks ++ + new WithFireSimHighPerfClocking ++ new WithFireSimDesignTweaks ) @@ -254,11 +222,6 @@ class FireSimCVA6Config extends Config( //********************************************************************************** //* Multiclock Configurations //*********************************************************************************/ -class FireSimMulticlockRocketConfig extends Config( - new chipyard.config.WithTileFrequency(6000.0) ++ //lol - new freechips.rocketchip.subsystem.WithRationalRocketTiles ++ // Add rational crossings between RocketTile and uncore - new FireSimRocketConfig) - class FireSimMulticlockAXIOverSerialConfig extends Config( new WithAXIOverSerialTLCombinedBridges ++ // use combined bridge to connect to axi mem over serial new WithDefaultFireSimBridges ++ diff --git a/generators/firechip/src/test/scala/ScalaTestSuite.scala b/generators/firechip/src/test/scala/ScalaTestSuite.scala index 64b217b8..397f23d4 100644 --- a/generators/firechip/src/test/scala/ScalaTestSuite.scala +++ b/generators/firechip/src/test/scala/ScalaTestSuite.scala @@ -107,11 +107,6 @@ abstract class FireSimTestSuite( class RocketF1Tests extends FireSimTestSuite("FireSim", "DDR3FRFCFSLLC4MB_FireSimQuadRocketConfig", "WithSynthAsserts_BaseF1Config") class BoomF1Tests extends FireSimTestSuite("FireSim", "DDR3FRFCFSLLC4MB_FireSimLargeBoomConfig", "BaseF1Config") class RocketNICF1Tests extends FireSimTestSuite("FireSim", "WithNIC_DDR3FRFCFSLLC4MB_FireSimRocketConfig", "BaseF1Config") -// Multiclock tests -class RocketMulticlockF1Tests extends FireSimTestSuite( - "FireSim", - "FireSimMulticlockRocketConfig", - "WithSynthAsserts_BaseF1Config") class CVA6F1Tests extends FireSimTestSuite("FireSim", "WithNIC_DDR3FRFCFSLLC4MB_FireSimCVA6Config", "BaseF1Config") @@ -119,5 +114,4 @@ class CVA6F1Tests extends FireSimTestSuite("FireSim", "WithNIC_DDR3FRFCFSLLC4MB_ class CITests extends Suites( new RocketF1Tests, new BoomF1Tests, - new RocketNICF1Tests, - new RocketMulticlockF1Tests) + new RocketNICF1Tests)