renamed clock_clock to clock_uncore_clock

2023-06-30 15:04:38 -07:00
parent dcaca02e14
commit 222059941e
7 changed files with 8 additions and 8 deletions
--- a/vlsi/example-designs/sky130-openroad.yml
+++ b/vlsi/example-designs/sky130-openroad.yml
@@ -3,7 +3,7 @@
 # Specify clock signals
 # Relax the clock period for OpenROAD to meet timing
 vlsi.inputs.clocks: [
-  {name: "clock_clock", period: "50ns", uncertainty: "2ns"}
+  {name: "clock_uncore_clock", period: "50ns", uncertainty: "2ns"}
 ]

 # Flow parameters that yield a routable design with reasonable timing