diff --git a/generators/chipyard/src/main/scala/ConfigFragments.scala b/generators/chipyard/src/main/scala/ConfigFragments.scala index d7becac6..e66dfb4a 100644 --- a/generators/chipyard/src/main/scala/ConfigFragments.scala +++ b/generators/chipyard/src/main/scala/ConfigFragments.scala @@ -5,13 +5,13 @@ import chisel3.util.{log2Up} import freechips.rocketchip.config.{Field, Parameters, Config} import freechips.rocketchip.subsystem._ -import freechips.rocketchip.diplomacy.{LazyModule, ValName} +import freechips.rocketchip.diplomacy._ import freechips.rocketchip.devices.tilelink.{BootROMLocated} import freechips.rocketchip.devices.debug.{Debug, ExportDebug, DebugModuleKey, DMI} import freechips.rocketchip.groundtest.{GroundTestSubsystem} import freechips.rocketchip.tile._ import freechips.rocketchip.rocket.{RocketCoreParams, MulDivParams, DCacheParams, ICacheParams} -import freechips.rocketchip.util.{AsyncResetReg} +import freechips.rocketchip.util.{AsyncResetReg, Symmetric} import freechips.rocketchip.prci._ import testchipip._ @@ -172,3 +172,46 @@ class WithPeripheryBusFrequencyAsDefault extends Config((site, here, up) => { case DefaultClockFrequencyKey => (site(PeripheryBusKey).dtsFrequency.get / (1000 * 1000)).toDouble }) +/** + * Mixins to specify crossing types between the 5 traditional TL buses + * + * Note: these presuppose the legacy connections between buses and set + * parameters in SubsystemCrossingParams; they may not be resuable in custom + * topologies (but you can specify the desired crossings in your topology). + * + * @param xType The clock crossing type + * + */ + +class WithSbusToMbusCrossingType(xType: ClockCrossingType) extends Config((site, here, up) => { + case SbusToMbusXTypeKey => xType +}) +class WithSbusToCbusCrossingType(xType: ClockCrossingType) extends Config((site, here, up) => { + case SbusToCbusXTypeKey => xType +}) +class WithCbusToPbusCrossingType(xType: ClockCrossingType) extends Config((site, here, up) => { + case CbusToPbusXTypeKey => xType +}) +class WithFbusToSbusCrossingType(xType: ClockCrossingType) extends Config((site, here, up) => { + case FbusToSbusXTypeKey => xType +}) + +/** + * Mixins to set the dtsFrequency field of BusParams -- these will percolate its way + * up the diplomatic graph to the clock sources. + */ +class WithPeripheryBusFrequency(freqMHz: Double) extends Config((site, here, up) => { + case PeripheryBusKey => up(PeripheryBusKey).copy(dtsFrequency = Some(BigInt((freqMHz * 1e6).toLong))) +}) +class WithMemoryBusFrequency(freqMHz: Double) extends Config((site, here, up) => { + case MemoryBusKey => up(MemoryBusKey).copy(dtsFrequency = Some(BigInt((freqMHz * 1e6).toLong))) +}) +class WithSystemBusFrequency(freqMHz: Double) extends Config((site, here, up) => { + case SystemBusKey => up(SystemBusKey).copy(dtsFrequency = Some(BigInt((freqMHz * 1e6).toLong))) +}) +class WithControlBusFrequency(freqMHz: Double) extends Config((site, here, up) => { + case ControlBusKey => up(ControlBusKey).copy(dtsFrequency = Some(BigInt((freqMHz * 1e6).toLong))) +}) + +class WithRationalMemoryBusCrossing extends WithSbusToMbusCrossingType(RationalCrossing(Symmetric)) +class WithAsynchrousMemoryBusCrossing extends WithSbusToMbusCrossingType(AsynchronousCrossing()) diff --git a/generators/chipyard/src/main/scala/CustomBusTopologies.scala b/generators/chipyard/src/main/scala/CustomBusTopologies.scala index 5dbcfe1d..c1c09285 100644 --- a/generators/chipyard/src/main/scala/CustomBusTopologies.scala +++ b/generators/chipyard/src/main/scala/CustomBusTopologies.scala @@ -16,12 +16,14 @@ import freechips.rocketchip.subsystem._ /** * Keys that serve as a means to define crossing types from a Parameters instance */ -case object SubsystemCrossingParamsKey extends Field[SubsystemCrossingParams](SubsystemCrossingParams()) -case object MemoryBusCrossingTypeKey extends Field[ClockCrossingType](NoCrossing) +case object SbusToMbusXTypeKey extends Field[ClockCrossingType](NoCrossing) +case object SbusToCbusXTypeKey extends Field[ClockCrossingType](NoCrossing) +case object CbusToPbusXTypeKey extends Field[ClockCrossingType](SynchronousCrossing()) +case object FbusToSbusXTypeKey extends Field[ClockCrossingType](SynchronousCrossing()) // Biancolin: This, modified from Henry's email /** Parameterization of a topology containing a banked coherence manager and a bus for attaching memory devices. */ -case class CoherentBusTopologyParams( +case class CoherentMulticlockBusTopologyParams( sbus: SystemBusParams, // TODO remove this after better width propagation mbus: MemoryBusParams, l2: BankedL2Params, @@ -41,60 +43,20 @@ case class CoherentBusTopologyParams( // For subsystem/Configs.scala -class WithCoherentBusTopology extends Config((site, here, up) => { +class WithMulticlockCoherentBusTopology extends Config((site, here, up) => { case TLNetworkTopologyLocated(InSubsystem) => List( JustOneBusTopologyParams(sbus = site(SystemBusKey)), HierarchicalBusTopologyParams( pbus = site(PeripheryBusKey), fbus = site(FrontBusKey), cbus = site(ControlBusKey), - xTypes = SubsystemCrossingParams()), - CoherentBusTopologyParams( + xTypes = SubsystemCrossingParams( + sbusToCbusXType = site(SbusToCbusXTypeKey), + cbusToPbusXType = site(CbusToPbusXTypeKey), + fbusToSbusXType = site(FbusToSbusXTypeKey))), + CoherentMulticlockBusTopologyParams( sbus = site(SystemBusKey), mbus = site(MemoryBusKey), l2 = site(BankedL2Key), - sbusToMbusXType = site(MemoryBusCrossingTypeKey))) + sbusToMbusXType = site(SbusToMbusXTypeKey))) }) - -/** - * Mixins to specify crossing types between the 5 traditional TL buses - * - * Note: these presuppose the legacy connections between buses and set - * parameters in SubsystemCrossingParams; they may not be resuable in custom - * topologies (but you can specify the desired crossings in your topology). - * - * @param xType The clock crossing type - * - */ -class WithMemoryBusCrossingType(xType: ClockCrossingType) extends Config((site, here, up) => { - case MemoryBusCrossingTypeKey => xType -}) - -class WithFrontBusCrossingType(xType: ClockCrossingType) extends Config((site, here, up) => { - case SubsystemCrossingParamsKey => up(SubsystemCrossingParamsKey, site) - .copy(fbusToSbusXType = xType) -}) - -class WithControlBusCrossingType(xType: ClockCrossingType) extends Config((site, here, up) => { - case SubsystemCrossingParamsKey => up(SubsystemCrossingParamsKey, site) - .copy(sbusToCbusXType = xType) -}) - -class WithPeripheryBusCrossingType(xType: ClockCrossingType) extends Config((site, here, up) => { - case SubsystemCrossingParamsKey => up(SubsystemCrossingParamsKey, site) - .copy(cbusToPbusXType = xType) -}) - -/** - * Mixins to set the dtsFrequency field of BusParams -- these will percolate it'st way - * through the diplomatic clock graph to the clock sources. - */ -class WithPeripheryBusFrequency(freq: BigInt) extends Config((site, here, up) => { - case PeripheryBusKey => up(PeripheryBusKey).copy(dtsFrequency = Some(freq)) -}) -class WithMemoryBusFrequency(freq: BigInt) extends Config((site, here, up) => { - case MemoryBusKey => up(MemoryBusKey).copy(dtsFrequency = Some(freq)) -}) - -class WithRationalMemoryBusCrossing extends WithMemoryBusCrossingType(RationalCrossing(Symmetric)) -class WithAsynchrousMemoryBusCrossing extends WithMemoryBusCrossingType(AsynchronousCrossing()) diff --git a/generators/chipyard/src/main/scala/IOBinders.scala b/generators/chipyard/src/main/scala/IOBinders.scala index 1ba6c0a9..8537b418 100644 --- a/generators/chipyard/src/main/scala/IOBinders.scala +++ b/generators/chipyard/src/main/scala/IOBinders.scala @@ -112,6 +112,8 @@ object BoreHelper { val (io, wire) = source match { case c: Clock => val wire = Wire(Clock()) + // Provide a dummy assignment to prevent FIRRTL invalid assignment + // errors prior to running the wiring pass wire := false.B.asClock (IO(Output(Clock())), wire) case r: Reset => @@ -269,8 +271,9 @@ class WithAXI4MemPunchthrough extends OverrideIOBinder({ val ports: Seq[ClockedAndResetIO[AXI4Bundle]] = system.mem_axi4.zipWithIndex.map({ case (m, i) => val p = IO(new ClockedAndResetIO(DataMirror.internal.chiselTypeClone[AXI4Bundle](m))).suggestName(s"axi4_mem_${i}") p.bits <> m - p.clock := BoreHelper("axi4_mem_clock", system.asInstanceOf[BaseSubsystem].mbus.module.clock) - p.reset := BoreHelper("axi4_mem_reset", system.asInstanceOf[BaseSubsystem].mbus.module.reset) + val mbus = system.asInstanceOf[HasTileLinkLocations].locateTLBusWrapper(MBUS) + p.clock := BoreHelper("axi4_mem_clock", mbus.module.clock) + p.reset := BoreHelper("axi4_mem_reset", mbus.module.reset) p }) (ports, Nil) diff --git a/generators/chipyard/src/main/scala/config/AbstractConfig.scala b/generators/chipyard/src/main/scala/config/AbstractConfig.scala index c4b1c9cf..301c03d7 100644 --- a/generators/chipyard/src/main/scala/config/AbstractConfig.scala +++ b/generators/chipyard/src/main/scala/config/AbstractConfig.scala @@ -49,6 +49,6 @@ class AbstractConfig extends Config( new freechips.rocketchip.subsystem.WithNoSlavePort ++ // no top-level MMIO slave port (overrides default set in rocketchip) new freechips.rocketchip.subsystem.WithInclusiveCache ++ // use Sifive L2 cache new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ // no external interrupts - new chipyard.WithCoherentBusTopology ++ // hierarchical buses including mbus+l2 + new chipyard.WithMulticlockCoherentBusTopology ++ // hierarchical buses including mbus+l2 new freechips.rocketchip.system.BaseConfig) // "base" rocketchip system diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala index e89727f1..a056ec32 100644 --- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala +++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala @@ -178,8 +178,9 @@ class DividedClockRocketConfig extends Config( new chipyard.config.WithTileFrequency(200.0) ++ new freechips.rocketchip.subsystem.WithRationalRocketTiles ++ // Add rational crossings between RocketTile and uncore new freechips.rocketchip.subsystem.WithNBigCores(1) ++ - new chipyard.WithMemoryBusFrequency(50 * 1000 * 1000) ++ - new chipyard.WithAsynchrousMemoryBusCrossing ++ + new chipyard.config.WithMemoryBusFrequency(50.0) ++ + new chipyard.config.WithAsynchrousMemoryBusCrossing ++ + new testchipip.WithAsynchronousSerialSlaveCrossing ++ new chipyard.config.AbstractConfig) class LBWIFRocketConfig extends Config( diff --git a/generators/firechip/src/main/scala/FireSim.scala b/generators/firechip/src/main/scala/FireSim.scala index cfca74f8..15defa66 100644 --- a/generators/firechip/src/main/scala/FireSim.scala +++ b/generators/firechip/src/main/scala/FireSim.scala @@ -96,7 +96,7 @@ class WithFireSimSimpleClocks extends Config((site, here, up) => { val aggregator = LazyModule(new ClockGroupAggregator("allClocks")).node (chiptop.implicitClockSinkNode := ClockGroup() := aggregator) - (systemAsyncClockGroup := ClockGroupNamePrefixer() := aggregator) + (systemAsyncClockGroup :*= ClockGroupNamePrefixer() :*= aggregator) val inputClockSource = ClockGroupSourceNode(Seq(ClockGroupSourceParameters())) diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala index 6ff5065f..ee231419 100644 --- a/generators/firechip/src/main/scala/TargetConfigs.scala +++ b/generators/firechip/src/main/scala/TargetConfigs.scala @@ -37,10 +37,6 @@ class WithBootROM extends Config((site, here, up) => { } }) -class WithPeripheryBusFrequency(freq: BigInt) extends Config((site, here, up) => { - case PeripheryBusKey => up(PeripheryBusKey).copy(dtsFrequency = Some(freq)) -}) - // Disables clock-gating; doesn't play nice with our FAME-1 pass class WithoutClockGating extends Config((site, here, up) => { case DebugModuleKey => up(DebugModuleKey, site).map(_.copy(clockGate = false)) @@ -72,13 +68,15 @@ class WithFireSimConfigTweaks extends Config( new WithBootROM ++ // Optional*: Removing this will require adjusting the UART baud rate and // potential target-software changes to properly capture UART output - new WithPeripheryBusFrequency(BigInt(3200000000L)) ++ - // Optional: Removing these two configs will result in the FASED timing model running + new chipyard.config.WithPeripheryBusFrequency(3200.0) ++ + // Optional: These three configs put the DRAM memory system in it's own clock domian. + // Removing the first config will result in the FASED timing model running // at the pbus freq (above, 3.2 GHz), which is outside the range of valid DDR3 speedgrades. // 1 GHz matches the FASED default, using some other frequency will require // runnings the FASED runtime configuration generator to generate faithful DDR3 timing values. - new chipyard.config.WithMemoryBusFrequency(1000 * 1000 * 1000) ++ + new chipyard.config.WithMemoryBusFrequency(1000.0) ++ new chipyard.config.WithAsynchrousMemoryBusCrossing ++ + new testchipip.WithAsynchronousSerialSlaveCrossing ++ // Required: Existing FAME-1 transform cannot handle black-box clock gates new WithoutClockGating ++ // Required*: Removes thousands of assertions that would be synthesized (* pending PriorityMux bugfix) @@ -133,7 +131,7 @@ class FireSimSmallSystemConfig extends Config( new WithDefaultFireSimBridges ++ new WithDefaultMemModel ++ new WithBootROM ++ - new WithPeripheryBusFrequency(BigInt(3200000000L)) ++ + new chipyard.WithPeripheryBusFrequency(3200.0) ++ new WithoutClockGating ++ new WithoutTLMonitors ++ new freechips.rocketchip.subsystem.WithExtMemSize(1 << 28) ++ diff --git a/generators/testchipip b/generators/testchipip index b3987a3a..51240a9a 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit b3987a3a784c7175c81aa58016fb3e2df58924c2 +Subproject commit 51240a9a892e871a20f3038ea6bc4293318d73db