Explicitly provide refClockFreqMHz to harnessClockInstantiator

2023-05-13 11:18:03 -07:00
parent a89b86c785
commit 2077e4304d
10 changed files with 23 additions and 7 deletions
--- a/fpga/src/main/scala/vc707/TestHarness.scala
+++ b/fpga/src/main/scala/vc707/TestHarness.scala
@@ -114,6 +114,7 @@ class VC707FPGATestHarnessImp(_outer: VC707FPGATestHarness) extends LazyRawModul
  val hReset = Wire(Reset())
  hReset := _outer.dutClock.in.head._1.reset

+  def referenceClockFreqMHz = _outer.dutFreqMHz
  def referenceClock = _outer.dutClock.in.head._1.clock
  def referenceReset = hReset
  def success = { require(false, "Unused"); false.B }